A. Chattopadhyay, L. Amarù, Mathias Soeken, P. Gaillardon, G. Micheli
{"title":"多数布尔代数注释","authors":"A. Chattopadhyay, L. Amarù, Mathias Soeken, P. Gaillardon, G. Micheli","doi":"10.1109/ISMVL.2016.21","DOIUrl":null,"url":null,"abstract":"A Majority-Inverter Graph (MIG) is a homogeneous logic network, where each node represents the majority function. Recently, a logic optimization package based on the MIG data structure, with 3-input majority node (M3) has been proposed [2],[30]. It is demonstrated to have efficient area-delay-power results compared to state-of-the-art logic optimization packages. In this paper, the Boolean algebraic transformations based on majority logic, i.e., majority Boolean algebra is studied. In the first part of this paper, we summarize a range of identities for majority Boolean algebra with their corresponding proofs. In the second part, we venture towards heterogeneous logic network and provide reversible logic mapping of majority nodes.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Notes on Majority Boolean Algebra\",\"authors\":\"A. Chattopadhyay, L. Amarù, Mathias Soeken, P. Gaillardon, G. Micheli\",\"doi\":\"10.1109/ISMVL.2016.21\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Majority-Inverter Graph (MIG) is a homogeneous logic network, where each node represents the majority function. Recently, a logic optimization package based on the MIG data structure, with 3-input majority node (M3) has been proposed [2],[30]. It is demonstrated to have efficient area-delay-power results compared to state-of-the-art logic optimization packages. In this paper, the Boolean algebraic transformations based on majority logic, i.e., majority Boolean algebra is studied. In the first part of this paper, we summarize a range of identities for majority Boolean algebra with their corresponding proofs. In the second part, we venture towards heterogeneous logic network and provide reversible logic mapping of majority nodes.\",\"PeriodicalId\":246194,\"journal\":{\"name\":\"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2016.21\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2016.21","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Majority-Inverter Graph (MIG) is a homogeneous logic network, where each node represents the majority function. Recently, a logic optimization package based on the MIG data structure, with 3-input majority node (M3) has been proposed [2],[30]. It is demonstrated to have efficient area-delay-power results compared to state-of-the-art logic optimization packages. In this paper, the Boolean algebraic transformations based on majority logic, i.e., majority Boolean algebra is studied. In the first part of this paper, we summarize a range of identities for majority Boolean algebra with their corresponding proofs. In the second part, we venture towards heterogeneous logic network and provide reversible logic mapping of majority nodes.