An optimized two stages low power sinc3 filter for ΣΔ modulators

This paper presents the design of a low power sinc3 filter implementing a decimation factor by 16 and suitable for a second order SigmaDelta modulators running at 256 MHz. The circuit uses the cascade of two stages and consumes only 48.1 muW, with 1.2 V voltage supply. The ultra-low power features come from both an architectural optimization and the use of suitable transistor level schemes. The circuit, simulated in a 0.18-mum CMOS technology, improves the overall power consumption by about 75.4% with respect to an already optimum conventional design.