Design and FPGA implementation of a real-time processor for the HDR conversion of images and videos

In this paper a multiresolution architecture to expand the dynamic range of low dynamic range (LDR) images to 32-bit high dynamic range (HDR) counterpart is presented. The processor is capable to provide on-the-fly calculation of the edge-preserving bilateral filtering and luminance average, to images images up to full-HD images (1920×1080 pixels) using 25×9 filtering and up to 4K UHDTV images (3840×2160 pixels) using 25×5 filtering without frame buffers. To this end, a “hardware friendly” algorithm has been derived from the most effective methods presented in the literature. Additionally, the proposed design is capable of processing the input pixel in streaming order, as they come from input devices by avoiding frame buffers and eliminating external DRAM. The processor complexity can be configured with different area/speed ratios in order to meet the requirements of different FPGA platforms. Implemented on a high-end FPGA the processor achieves state-of-the art performances.