New fast disparity estimation algorithm by diminishing search range and fpga implementation

R ~ pixel ,r x + s x .r + s Abstract This paper pre.sent.s lieu' .fa.st dirparih, estimation algorithm by diminishing search range and fhe de.sign of' the real-time di,spari~ estimation pruces.sor. The prupsed algurithm i.vn 't un/v able 10 rediire the cumpntafiunul load ofdisporifv estirnafion hut also the size of harditwe isliile rvtoining good pevJimiiance. The hardware architecture ./iir the pmressor is proposed and ~ i ~ a s simulated in Verilog HDL. The procersor IWIS iniplemented on FPGA chip and is composed ofahout 180K logic gate.7. The di.7puriw maps of the proce,ssor tliat con rrrhieve over 60fi-ame.s per second for XGA (1024 h?, 7681 wew ranked 26th on the Middlebiriv stereo dutabase with gruntid trvrh'.