{"title":"采用0.18 /spl μ l /m CMOS技术的低功耗全差分2.4 ghz预分频器","authors":"S. Machan","doi":"10.1109/IWSOC.2003.1213014","DOIUrl":null,"url":null,"abstract":"A fully differential 2.4-GHz 8/9 dual modulus prescaler is presented in this paper. The circuit has been constructed in a 0.18 /spl mu/m 1.8 V CMOS process for use in a low-power ISM transceiver. The prescaler consists of internal buffering, the divider itself, a differential to CMOS converter, and a self-contained current source. Simulations imply a maximum operating frequency of 3.05 GHz which is the measurement of the silicon support. Its simulated current drain is 2.5 mA and it occupies an area of 130 /spl mu/m /spl times/ 60 /spl mu/m.","PeriodicalId":259178,"journal":{"name":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A low-power fully differential 2.4-GHz prescaler in 0.18 /spl mu/m CMOS technology\",\"authors\":\"S. Machan\",\"doi\":\"10.1109/IWSOC.2003.1213014\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully differential 2.4-GHz 8/9 dual modulus prescaler is presented in this paper. The circuit has been constructed in a 0.18 /spl mu/m 1.8 V CMOS process for use in a low-power ISM transceiver. The prescaler consists of internal buffering, the divider itself, a differential to CMOS converter, and a self-contained current source. Simulations imply a maximum operating frequency of 3.05 GHz which is the measurement of the silicon support. Its simulated current drain is 2.5 mA and it occupies an area of 130 /spl mu/m /spl times/ 60 /spl mu/m.\",\"PeriodicalId\":259178,\"journal\":{\"name\":\"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-07-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSOC.2003.1213014\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2003.1213014","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-power fully differential 2.4-GHz prescaler in 0.18 /spl mu/m CMOS technology
A fully differential 2.4-GHz 8/9 dual modulus prescaler is presented in this paper. The circuit has been constructed in a 0.18 /spl mu/m 1.8 V CMOS process for use in a low-power ISM transceiver. The prescaler consists of internal buffering, the divider itself, a differential to CMOS converter, and a self-contained current source. Simulations imply a maximum operating frequency of 3.05 GHz which is the measurement of the silicon support. Its simulated current drain is 2.5 mA and it occupies an area of 130 /spl mu/m /spl times/ 60 /spl mu/m.
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