基于DLL的温度补偿MEMS时钟

A. Rantala, D. G. Martins, M. Sopanen, M. Åberg
{"title":"基于DLL的温度补偿MEMS时钟","authors":"A. Rantala, D. G. Martins, M. Sopanen, M. Åberg","doi":"10.1109/NORCHIP.2010.5669492","DOIUrl":null,"url":null,"abstract":"In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented. The system is providing a temperature compensated 48 MHz clock signal for the range of − 40 to 85 °C. The temperature compensation is achieved by a combination of initial and an autonomous background calibration. The main design guidelines have been on high integration level and minimum silicon area while maintaining a low timing jitter and power consumption. The design was implemented by utilizing Austria Micro Systems (AMS) 0.35 µm standard CMOS process technology. The implementation occupies 1.75 mm2 of silicon area.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"DLL based temperature compensated MEMS clock\",\"authors\":\"A. Rantala, D. G. Martins, M. Sopanen, M. Åberg\",\"doi\":\"10.1109/NORCHIP.2010.5669492\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented. The system is providing a temperature compensated 48 MHz clock signal for the range of − 40 to 85 °C. The temperature compensation is achieved by a combination of initial and an autonomous background calibration. The main design guidelines have been on high integration level and minimum silicon area while maintaining a low timing jitter and power consumption. The design was implemented by utilizing Austria Micro Systems (AMS) 0.35 µm standard CMOS process technology. The implementation occupies 1.75 mm2 of silicon area.\",\"PeriodicalId\":292342,\"journal\":{\"name\":\"NORCHIP 2010\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"NORCHIP 2010\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORCHIP.2010.5669492\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"NORCHIP 2010","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHIP.2010.5669492","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

本文提出了一种基于锁滞环的温度补偿MEMS时钟的设计与实现。系统提供温度补偿48mhz时钟信号,工作范围为- 40至85°C。温度补偿是通过初始和自主背景校准的结合来实现的。主要的设计准则是高集成度和最小的硅面积,同时保持低时序抖动和功耗。该设计采用奥地利微系统公司(AMS) 0.35µm标准CMOS工艺技术实现。该实现占用1.75 mm2的硅面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
DLL based temperature compensated MEMS clock
In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented. The system is providing a temperature compensated 48 MHz clock signal for the range of − 40 to 85 °C. The temperature compensation is achieved by a combination of initial and an autonomous background calibration. The main design guidelines have been on high integration level and minimum silicon area while maintaining a low timing jitter and power consumption. The design was implemented by utilizing Austria Micro Systems (AMS) 0.35 µm standard CMOS process technology. The implementation occupies 1.75 mm2 of silicon area.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
SOC chip scheduler embodying I-slip algorithm Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs Wideband inductorless LNA employing simultaneous 2nd and 3rd order distortion cancellation Application Of medium-grain multiprocessor mapping methodology to epileptic seizure predictor Calibration of ΣΔ analog-to-digital converters based on histogram test methods
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1