Novel Obfuscated Secure Architecture for Baugh Wooley Multiplier

The internationalisation of the semiconductor supply chain brings with it an increase in the hazards posed to both data security and physical security. Theft of intellectual property through reverse engineering and harmful design alterations are two primary threats. The latter is supported, in part, by the fruitful use of reverse engineering to the design. Two of the strategies that are currently under investigation to prevent reverse engineering by end users or foundries are known as IC stealth and logic blocking. Nonetheless, for a number of years, one of the most difficult challenges has been the creation of low-overload camouflage and blocking schemes that are resilient enough to endure the ever-changing condition of heart attacks. This article describes a unique design for a disguised multiplier as well as an implementation of that architecture. The structure that has been suggested is capable of being reorganised to compute an S-bit Baugh-Wooley multiplier. To conceal obfuscation modes, a fresh control flow method has been developed and implemented. When compared to the original design, it has been demonstrated that the suggested method results in space and power needs that are significantly reduced.