{"title":"一种低功耗数字信号处理器","authors":"H. Jang, S. Kim, Young-hoon Chang","doi":"10.1109/APASIC.1999.824025","DOIUrl":null,"url":null,"abstract":"Low power in digital signal processor design has been a critical design constraint since portable battery operated devices prevailed. Most of the power dissipation of a processor is in the clock network and the on-chip memory. By optimizing the critical path of the processor we could reduce the power of clock network. We propose an energy-efficient instruction set architecture to reduce the power consumption of the program memory access. We applied it to a digital hearing aid, and reduced the program memory size by approximately 75%.","PeriodicalId":346808,"journal":{"name":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A digital signal processor for low power\",\"authors\":\"H. Jang, S. Kim, Young-hoon Chang\",\"doi\":\"10.1109/APASIC.1999.824025\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Low power in digital signal processor design has been a critical design constraint since portable battery operated devices prevailed. Most of the power dissipation of a processor is in the clock network and the on-chip memory. By optimizing the critical path of the processor we could reduce the power of clock network. We propose an energy-efficient instruction set architecture to reduce the power consumption of the program memory access. We applied it to a digital hearing aid, and reduced the program memory size by approximately 75%.\",\"PeriodicalId\":346808,\"journal\":{\"name\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.1999.824025\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.1999.824025","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low power in digital signal processor design has been a critical design constraint since portable battery operated devices prevailed. Most of the power dissipation of a processor is in the clock network and the on-chip memory. By optimizing the critical path of the processor we could reduce the power of clock network. We propose an energy-efficient instruction set architecture to reduce the power consumption of the program memory access. We applied it to a digital hearing aid, and reduced the program memory size by approximately 75%.
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