高性能FPGA封装中高密度IO走线串扰的有效模拟方法

Wai Ling Lee, Hoon Ngik Low, Hong Shi
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引用次数: 0

摘要

本文提出了一种基于串扰叠加理论的快速串扰估计方法。本研究选择了一个现有的FPGA器件封装作为实际测试用例。采用Ansoft SI2D提取器对微带线和带状线的设计进行建模,并将提取的互矩阵模型用于Agilent Advance Design System (ADS)的串扰仿真。然后将串扰仿真结果与采用新串扰估计方法计算的串扰结果进行了比较。我们通过评估该方法在高IO密度FPGA封装中的有效性和适用性来总结本文。
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Effective method to simulate Crosstalk between high density IO traces in high performance FPGA packages
In this Paper, we propose a Quick Crosstalk Estimation Methodology by using Crosstalk Superposition Theory. An existing FPGA device package was chosen as the real test case for this study. For both microstrip and stripline, the designs were modeled by using Ansoft SI2D extractor, and the mutual matrix models extracted were used in crosstalk simulation conducted by using Agilent Advance Design System (ADS). The crosstalk simulation results were then compared with the crosstalk results calculated by using the new crosstalk estimation method. We summarize this paper by evaluate the effectiveness and applicability of this proposed methodology in FPGA package with high IO density.
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