一种新的高效FPGA路由算法

2007 2nd IEEE Conference on Industrial Electronics and Applications Pub Date : 2007-09-24 DOI:10.1109/ICIEA.2007.4318642

Z. Liu, Zong-guang Yu, Xiaofeng Gu

{"title":"一种新的高效FPGA路由算法","authors":"Z. Liu, Zong-guang Yu, Xiaofeng Gu","doi":"10.1109/ICIEA.2007.4318642","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a new and efficient hybrid Routing algorithm for FPGAs by integrating a Boolean satisfiability algorithm with geometric routing algorithm. It takes advantage of the rip-up-reroute capabilities of the conventional geometric routing algorithm and simultaneous net embedding characteristic of Boolean SAT-based FPGA routing. Experiment results show that compared with the corresponding pure geometric routing algorithm, the running time is dramatic reduced.","PeriodicalId":231682,"journal":{"name":"2007 2nd IEEE Conference on Industrial Electronics and Applications","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A New and Efficient Algorithm for FPGA Routing\",\"authors\":\"Z. Liu, Zong-guang Yu, Xiaofeng Gu\",\"doi\":\"10.1109/ICIEA.2007.4318642\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a new and efficient hybrid Routing algorithm for FPGAs by integrating a Boolean satisfiability algorithm with geometric routing algorithm. It takes advantage of the rip-up-reroute capabilities of the conventional geometric routing algorithm and simultaneous net embedding characteristic of Boolean SAT-based FPGA routing. Experiment results show that compared with the corresponding pure geometric routing algorithm, the running time is dramatic reduced.\",\"PeriodicalId\":231682,\"journal\":{\"name\":\"2007 2nd IEEE Conference on Industrial Electronics and Applications\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 2nd IEEE Conference on Industrial Electronics and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIEA.2007.4318642\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 2nd IEEE Conference on Industrial Electronics and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIEA.2007.4318642","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

本文将布尔可满足性算法与几何路由算法相结合，提出了一种高效的fpga混合路由算法。它利用了传统几何路由算法的撕裂路由能力和基于布尔sat的FPGA路由同时嵌入网络的特点。实验结果表明，与相应的纯几何路由算法相比，该算法的运行时间大大缩短。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A New and Efficient Algorithm for FPGA Routing

In this paper, we propose a new and efficient hybrid Routing algorithm for FPGAs by integrating a Boolean satisfiability algorithm with geometric routing algorithm. It takes advantage of the rip-up-reroute capabilities of the conventional geometric routing algorithm and simultaneous net embedding characteristic of Boolean SAT-based FPGA routing. Experiment results show that compared with the corresponding pure geometric routing algorithm, the running time is dramatic reduced.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2007 2nd IEEE Conference on Industrial Electronics and Applications

自引率

0.00%

发文量