Design of a Delta Threshold Voltage Difference based fully Embedded Read Only Memory along with a Skew Sense Amplifier

This paper describes the design and implementation of an embedded ROM memory along with its sense amplifier. Several applications in machine learning have fixed data to be stored in a memory, which needs to be read out multiple times. Hence a fast, on-chip solution is proposed in this technical paper wherein logic transistors are used to design a read only memory with completely zero added process complexity. Several design constraints of sensing the ROM cell have been elaborated to a great extent. Also, a key advantage in the sense amplifier used is the ability to use all transistors from the same process technology. Further, by always fixing a MOS device in saturation and the other MOS device in cut off region, fast sensing is achieved at the sense amplifier output. The layout designed for the sense amplifier is verified to produce a very minimal deviation from the actual schematic simulations, hence suggesting a considerably well designed layout. The operating frequency of the sense amplifier is determined as 12.5 GHz with full swing resolution.