A collision-free time-to-first spike camera architecture based on a winner-take-all network

A new type of asynchronous time-based digital camera is here presented. The sensor architecture is characterized by a new analog low-power winner take all (WTA) network shared among all the pixels of the array. This circuit detects the most illuminated pixel and transmits it through the channel by queuing the other competitors. An iterative algorithm allows to read-out the entire array, temporally dispatching the information by means of an asynchronous read-out circuit placed at column and row level. The pixel, designed with a 0.35 mum CMOS technology and consisting of 28 transistors, performs a simulated average power consumption less than 10 nW @ 1.8 V for an impinging light power of 100 muW/cm2.