一种基于脉冲收缩/拉伸机制的低功率宽范围占空比校正器

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI:10.1109/ASSCC.2007.4425730

Poki Chen, Shi-Wei Chen, Juan-Shan Lai

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引用次数: 24

摘要

提出了一种基于脉冲收缩/拉伸机制的占空比校正器。所提出的DCC已在台积电0.35 μ m标准CMOS工艺中润滑。输入占空比范围为30%~70%。在3MHz~60MHz的最宽频率工作范围内，占空比误差在±1.0%以内，这使得电路最适合超宽带应用。芯片面积仅为0.3 × 0.2 mm2，功耗为1。1mW, 550mhz。

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A low power wide tange duty cycle corrector based on pulse shrinking/stretching mechanism

A duty cycle corrector based on pulse shrinking/ stretching mechanism is presented. The proposed DCC has been rubricated in a TSMC 0.35mum standard CMOS process. An input duty cycle range of 30%~70% is achieved. The duty cycle error is within plusmn1.0% for the widest frequency operation range of 3MHz~60MHz ever fulfilled which makes the circuit best suited for ultra wide band applications. The chip area is merely 0.3 x 0.2 mm2 and the power consumption is 1. 1mW at 550 MHz.

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2007 IEEE Asian Solid-State Circuits Conference

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