{"title":"输出预测逻辑在差分CMOS中的应用","authors":"Su Go, L. McMurchie, Carl Sechen","doi":"10.1109/IWV.2001.923140","DOIUrl":null,"url":null,"abstract":"We apply the output prediction logic (OPL) technique to the differential CMOS logic family. Including the effects of process, voltage and temperature (PVT) variations, we show that OPL differential CMOS is more than 40% faster than the single-rail OPL-dynamic logic family, and nearly 5 times faster than optimized static CMOS. We also demonstrate an OPL-differential 64:2 compressor that is 37% faster than the OPL-dynamic version. Finally, we show that OPL-differential is nearly twice as fast as differential domino.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Application of output prediction logic to differential CMOS\",\"authors\":\"Su Go, L. McMurchie, Carl Sechen\",\"doi\":\"10.1109/IWV.2001.923140\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We apply the output prediction logic (OPL) technique to the differential CMOS logic family. Including the effects of process, voltage and temperature (PVT) variations, we show that OPL differential CMOS is more than 40% faster than the single-rail OPL-dynamic logic family, and nearly 5 times faster than optimized static CMOS. We also demonstrate an OPL-differential 64:2 compressor that is 37% faster than the OPL-dynamic version. Finally, we show that OPL-differential is nearly twice as fast as differential domino.\",\"PeriodicalId\":114059,\"journal\":{\"name\":\"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-04-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWV.2001.923140\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWV.2001.923140","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Application of output prediction logic to differential CMOS
We apply the output prediction logic (OPL) technique to the differential CMOS logic family. Including the effects of process, voltage and temperature (PVT) variations, we show that OPL differential CMOS is more than 40% faster than the single-rail OPL-dynamic logic family, and nearly 5 times faster than optimized static CMOS. We also demonstrate an OPL-differential 64:2 compressor that is 37% faster than the OPL-dynamic version. Finally, we show that OPL-differential is nearly twice as fast as differential domino.
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