A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms

In this paper, a model of the bus power consumption able to predict the results of a multi-bit differential power attack (DPA) in symmetric-key cryptographic algorithm (e.g. AES, DES) is developed. The analytical results represent a theoretical basis to better understand the vulnerability to DPA attacks of cryptographic VLSI circuits. To the best of the authors' knowledge, this is the first paper that quantitatively evaluates the fundamental parameters that determine the effectiveness of DPA attacks to symmetric-key algorithms. The results are validated by means of SPICE simulations on the address bus of a MIPS32 architecture in a 0.18-mum CMOS technology, with the MIPS32 being modeled by an in-house cycle-accurate simulator.