2 GHz应用程序的domino合成的系统级解决方案

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI:10.1109/ICCD.2002.1106765

B. Chappell, Xinning Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain

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引用次数: 8

摘要

描述了多米诺骨牌合成能力的系统结构和带出的0.18u 2 GHz产品应用结果，该能力涵盖了多米诺骨牌设计的所有方面，从估计到硅就绪布局，并具有定制级优化。所描述的优化流程、抽象模式和关键成本因素可在复杂逻辑上实现功耗优化、噪声校正的多米诺骨牌性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A system-level solution to domino synthesis with 2 GHz application

System structure and a taped out 0.18u 2 GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.

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