{"title":"采用MTCMOS和自控电压电平电路的低功率脉冲触发d型触发器","authors":"Liaqat Moideen Parakundil, N. Saraswathi","doi":"10.1109/ICACCCT.2014.7019139","DOIUrl":null,"url":null,"abstract":"Reducing power consumption is a crucial task for any circuits. Increased demand for portable devices with reduced power dissipation has put necessary traction to design low power circuits. Both explicit and implicit pulse triggered flip flops are designed. Multiple Threshold CMOS (MTCMOS) technique and Self-controllable voltage level (SVL) circuit are employed to reduce power consumption. All the circuits are designed in 45nm technology for 1 GHz frequency.","PeriodicalId":239918,"journal":{"name":"2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Low power pulse triggered D-flip flops using MTCMOS and Self-controllable voltage level circuit\",\"authors\":\"Liaqat Moideen Parakundil, N. Saraswathi\",\"doi\":\"10.1109/ICACCCT.2014.7019139\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Reducing power consumption is a crucial task for any circuits. Increased demand for portable devices with reduced power dissipation has put necessary traction to design low power circuits. Both explicit and implicit pulse triggered flip flops are designed. Multiple Threshold CMOS (MTCMOS) technique and Self-controllable voltage level (SVL) circuit are employed to reduce power consumption. All the circuits are designed in 45nm technology for 1 GHz frequency.\",\"PeriodicalId\":239918,\"journal\":{\"name\":\"2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICACCCT.2014.7019139\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICACCCT.2014.7019139","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low power pulse triggered D-flip flops using MTCMOS and Self-controllable voltage level circuit
Reducing power consumption is a crucial task for any circuits. Increased demand for portable devices with reduced power dissipation has put necessary traction to design low power circuits. Both explicit and implicit pulse triggered flip flops are designed. Multiple Threshold CMOS (MTCMOS) technique and Self-controllable voltage level (SVL) circuit are employed to reduce power consumption. All the circuits are designed in 45nm technology for 1 GHz frequency.
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