55纳米嵌入式SuperFlash®技术2T存储单元的SPICE建模

S. Martinie, O. Rozeau, M. Tadayoni, C. Raynaud, E. Nowak, S. Hariharan, N. Do
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引用次数: 2

摘要

嵌入式Flash NVM已成为许多应用的关键组件,如数据处理、工业电子、汽车电子、消费电子和无线通信。SuperFlash®技术基于分栅概念,使用源端电子注入进行编程。这项工作的目的是首次提出在55纳米CMOS技术中实现的2T(选择门和浮门)第三代SuperFlash单元[Hidaka]的SPICE宏观模型。提出了一种参数提取方法,模型与实测结果吻合较好。
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SPICE modeling of 55 nm embedded SuperFlash® technology 2T memory cells
Embedded Flash NVM has become a key component in many applications, such as data processing, industrial electronics, automotive electronics, consumer electronics and wireless communications. SuperFlash® technology is based on the split-gate concept, using source-side electron injection for programming. The aim of this work is to propose, for the first time, a SPICE macro-model of the 2T (Select Gate and Floating Gate) 3rd generation SuperFlash cell [Hidaka], implemented in a 55 nm CMOS technology. A parameter extraction procedure is also proposed, showing a good agreement between the model and measurements.
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