一个1.3 μ m的BiCMOS门阵列，具有可配置的片上3端口RAM

Proceedings., Second Annual IEEE ASIC Seminar and Exhibit, Pub Date : 1989-09-25 DOI:10.1109/ASIC.1989.123187

T. Wong, M. El-Khatib

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摘要

采用1.3 μ m技术，研制了具有可配置4.6 kb SRAM(静态RAM)的10 k门BiCMOS门阵列。在0.6 pf负载下，双输入NAND的传输延迟时间为0.45 ns。片上存储器可以配置为*9、*18、* 36b。文中介绍了器件结构、基本单元设计、存储器配置以及这种存储器加逻辑组合的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 1.3 mu m BiCMOS gate array with configurable on-chip 3-port RAM

A 10 K-gate BiCMOS gate array with a configurable 4.6-kb SRAM (static RAM) has been developed using a 1.3- mu m technology. The propagation delay time of a two-input NAND is 0.45 ns at 0.6-pF load. The on-chip memory can be configured as *9, *18, *36 b. A description is given of the device structure, the basic cell design, the memory configuration, and the performance of this memory-plus-logic combination.<>

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Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,

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