{"title":"基于动态重映射集群的多核延迟感知容错缓存","authors":"A. Choudhury, Brototi Mondal, B. Sikdar","doi":"10.1109/ATS47505.2019.00014","DOIUrl":null,"url":null,"abstract":"This work proposes a re-usability aware fault remapping scheme for multicore NUCA cache. It replicates data in non-reusable blocks to ensure full error coverage and minimum latency, by forming dynamic remapping clusters around the home tiles. Simulations in Multi2Sim 5.0 claim up to 18.64% increase in hit ratio and 20.79% decrease in latency in last-level cache over the existing techniques with 3.17% area, 5.35% leakage power and 3.34% dynamic power overheads.","PeriodicalId":258824,"journal":{"name":"2019 IEEE 28th Asian Test Symposium (ATS)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Latency Aware Fault Tolerant Cache in Multicore Using Dynamic Remapping Clusters\",\"authors\":\"A. Choudhury, Brototi Mondal, B. Sikdar\",\"doi\":\"10.1109/ATS47505.2019.00014\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work proposes a re-usability aware fault remapping scheme for multicore NUCA cache. It replicates data in non-reusable blocks to ensure full error coverage and minimum latency, by forming dynamic remapping clusters around the home tiles. Simulations in Multi2Sim 5.0 claim up to 18.64% increase in hit ratio and 20.79% decrease in latency in last-level cache over the existing techniques with 3.17% area, 5.35% leakage power and 3.34% dynamic power overheads.\",\"PeriodicalId\":258824,\"journal\":{\"name\":\"2019 IEEE 28th Asian Test Symposium (ATS)\",\"volume\":\"172 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 28th Asian Test Symposium (ATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS47505.2019.00014\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 28th Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS47505.2019.00014","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Latency Aware Fault Tolerant Cache in Multicore Using Dynamic Remapping Clusters
This work proposes a re-usability aware fault remapping scheme for multicore NUCA cache. It replicates data in non-reusable blocks to ensure full error coverage and minimum latency, by forming dynamic remapping clusters around the home tiles. Simulations in Multi2Sim 5.0 claim up to 18.64% increase in hit ratio and 20.79% decrease in latency in last-level cache over the existing techniques with 3.17% area, 5.35% leakage power and 3.34% dynamic power overheads.