Scheduling and allocation for the high-level synthesis of DSP algorithms by exploitation of data transfer mobility

A scheduling and allocation method is given for the high-level synthesis of DSP algorithms described by iterative data flow graphs. The method is based on the concept of scheduling ranges. It generates overlapped schedules, while performing retiming and loop folding implicitly. The scheduler operates on the input and output data transfers of the operations in the graph, allowing a trade-off of functional units against buses. For each transfer a scheduling range is computed and the optimal position within this range is found by modified force-directed scheduling. The method has obtained optimal results for well-known benchmark examples.<>