{"title":"SNAP-1并行AI原型","authors":"R. Demara, D. Moldovan","doi":"10.1145/115952.115954","DOIUrl":null,"url":null,"abstract":"The Semantic Network Array Processor (SNAP) is a parallel architecture for Artificial Intelligence (AI) applications. We haue implemented a first-generation hardware/soflware prototype called SNAP-1 using Digital Signal Processor chips and ouerlapping groups of multiport memories. The design features 32 processing clusters with four to five functionally dedicated Digital Signal Processors in each cluster. Processors within clusters share a marker-processing memo y while communication between clusters is implemented by a buffered messagepassing scheme.","PeriodicalId":187095,"journal":{"name":"[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture","volume":"249 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":"{\"title\":\"The SNAP-1 parallel AI prototype\",\"authors\":\"R. Demara, D. Moldovan\",\"doi\":\"10.1145/115952.115954\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Semantic Network Array Processor (SNAP) is a parallel architecture for Artificial Intelligence (AI) applications. We haue implemented a first-generation hardware/soflware prototype called SNAP-1 using Digital Signal Processor chips and ouerlapping groups of multiport memories. The design features 32 processing clusters with four to five functionally dedicated Digital Signal Processors in each cluster. Processors within clusters share a marker-processing memo y while communication between clusters is implemented by a buffered messagepassing scheme.\",\"PeriodicalId\":187095,\"journal\":{\"name\":\"[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture\",\"volume\":\"249 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"34\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/115952.115954\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/115952.115954","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The Semantic Network Array Processor (SNAP) is a parallel architecture for Artificial Intelligence (AI) applications. We haue implemented a first-generation hardware/soflware prototype called SNAP-1 using Digital Signal Processor chips and ouerlapping groups of multiport memories. The design features 32 processing clusters with four to five functionally dedicated Digital Signal Processors in each cluster. Processors within clusters share a marker-processing memo y while communication between clusters is implemented by a buffered messagepassing scheme.
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