多重错误自检修复容错加法器

P. Palsodkar, P. Palsodkar, Rupali Giri
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引用次数: 5

摘要

人的行为有其局限性。在一些关键应用中,需要立即采取行动,如国防应用,空间相关,医疗器械或任何容错系统必不可少的安全应用。本文提出了一种新的全加法器(FA)实现容错加法器设计的方法,该方法比传统的方法更有效,具有抗多种误差的特点。本设计涵盖了自检测自修复FA,实现了对所有多重永久和瞬态错误的多重错误检测和修正能力。与之前实现的容错方法相比,这些加法器需要更低的面积开销和更少的功耗。面积开销分析表明,蜥蜴方法占面积开销的75%,部分三模冗余(PTMR)占面积开销的61%,而拟议的加法器100%没有面积开销。为进位选择加法器(CSA)设计的自检$FA$,与以前使用的自检CSA方法相比,消耗的面积减少了15%。与三模冗余(TMR)方法相比,该加法器的面积开销减少了25%,4位容错乘法器的功率延迟积减少了92%。
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Multiple Error Self Checking-Repairing Fault Tolerant Adder-Multiplier
Human action has its own limits. In some critical applications immediate action is required like defense application, space related, medical instruments or any safety application where fault tolerant systems are essential. This paper describes a new approach of full adder (FA) to accomplish fault-tolerant adder designs, which are more efficient than the conventional approaches, in distinct characteristic against many errors. This design covers self- checking and self-repairing FA to achieve multiple error detection and correction capability of all multiple permanent & transient errors. These adders require lower area overhead, less power consumption compared to the fault-tolerant methods implemented earlier. Area overhead analysis shows that the Lizard method consist of 75% of area overhead, Partial Triple Modular Redundancy (PTMR) consist an area overhead of 61% whereas the proposed adder is 100% free from area overhead. Self-checking $FA$, designed for carry select adder (CSA), consumes 15% less area compared to the previously used self-checking CSA approach. Area overhead of the proposed adder is 25% less, Power delay product of 4 bit fault tolerant multiplier is 92% less compared to Triple Modular Redundancy (TMR) method.
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