一种用于带内载波聚合的接收机架构

2014 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 2014-06-10 DOI:10.1109/VLSIC.2014.6858418

Sy-Chyuan Hwu, B. Razavi

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引用次数: 8

摘要

一种块下变频接收机包含数字图像抑制技术，通过一个接收路径和一个频率合成器支持多个聚合载波。由CMOS RF前端和FPGA后端组成的原型在2 GHz±25 MHz范围内显示出至少70 dB的图像抑制比(IRR)，并且在另一个高40 dB的通道存在时重建出-76 dbm的64-QAM信号，EVM为-30 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A receiver architecture for intra-band carrier aggregation

A block downconversion receiver incorporates a digital image rejection technique to support multiple aggregated carriers by one receive path and one frequency synthesizer. A prototype consisting of a CMOS RF front end and an FPGA back end exhibits an image rejection ratio (IRR) of at least 70 dB across 2 GHz ± 25 MHz and reconstructs a -76-dBm 64-QAM signal with an EVM of -30 dB in the presence of another channel 40 dB higher.

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2014 Symposium on VLSI Circuits Digest of Technical Papers

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