{"title":"基于门控存储器的片上监督学习策略","authors":"A. Rush, Alexander Jones, Eric Herrmann, R. Jha","doi":"10.1109/NAECON46414.2019.9057906","DOIUrl":null,"url":null,"abstract":"We report a gated-ReRAM synaptic devices-based strategy for on-chip supervised learning. A vacancy-driven compact model for gated-ReRAM is presented and corroborated with experimental results. A supervised learning architecture is proposed that allows the feedback to be provided via gate terminal of gated-ReRAM to update weights in a highly parallel manner.","PeriodicalId":193529,"journal":{"name":"2019 IEEE National Aerospace and Electronics Conference (NAECON)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Gated-ReRAM Based Strategies for On-Chip Supervised Learning\",\"authors\":\"A. Rush, Alexander Jones, Eric Herrmann, R. Jha\",\"doi\":\"10.1109/NAECON46414.2019.9057906\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report a gated-ReRAM synaptic devices-based strategy for on-chip supervised learning. A vacancy-driven compact model for gated-ReRAM is presented and corroborated with experimental results. A supervised learning architecture is proposed that allows the feedback to be provided via gate terminal of gated-ReRAM to update weights in a highly parallel manner.\",\"PeriodicalId\":193529,\"journal\":{\"name\":\"2019 IEEE National Aerospace and Electronics Conference (NAECON)\",\"volume\":\"98 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE National Aerospace and Electronics Conference (NAECON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NAECON46414.2019.9057906\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE National Aerospace and Electronics Conference (NAECON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON46414.2019.9057906","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Gated-ReRAM Based Strategies for On-Chip Supervised Learning
We report a gated-ReRAM synaptic devices-based strategy for on-chip supervised learning. A vacancy-driven compact model for gated-ReRAM is presented and corroborated with experimental results. A supervised learning architecture is proposed that allows the feedback to be provided via gate terminal of gated-ReRAM to update weights in a highly parallel manner.