{"title":"用FPGA实现LDPC编码器的近似下三角矩阵","authors":"Yi Hua Chen, Jue-Hsuan Hsiao, J. He","doi":"10.1109/GCCE.2012.6379546","DOIUrl":null,"url":null,"abstract":"This study used the weight (3, 6) approximate lower triangular regular parity check matrix to implement the LDPC encoding on the 5641R FPGA of the Software Define Radio system developed by National Instruments (NI) [1]. This study provided a detailed introduction to the encoding mechanism of the approximate lower triangular LDPC, and completed the implementation and verification of FPGA hardware.","PeriodicalId":299732,"journal":{"name":"The 1st IEEE Global Conference on Consumer Electronics 2012","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"FPGA implementation of LDPC encoder with approximate lower triangular matrix\",\"authors\":\"Yi Hua Chen, Jue-Hsuan Hsiao, J. He\",\"doi\":\"10.1109/GCCE.2012.6379546\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This study used the weight (3, 6) approximate lower triangular regular parity check matrix to implement the LDPC encoding on the 5641R FPGA of the Software Define Radio system developed by National Instruments (NI) [1]. This study provided a detailed introduction to the encoding mechanism of the approximate lower triangular LDPC, and completed the implementation and verification of FPGA hardware.\",\"PeriodicalId\":299732,\"journal\":{\"name\":\"The 1st IEEE Global Conference on Consumer Electronics 2012\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 1st IEEE Global Conference on Consumer Electronics 2012\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GCCE.2012.6379546\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 1st IEEE Global Conference on Consumer Electronics 2012","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GCCE.2012.6379546","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA implementation of LDPC encoder with approximate lower triangular matrix
This study used the weight (3, 6) approximate lower triangular regular parity check matrix to implement the LDPC encoding on the 5641R FPGA of the Software Define Radio system developed by National Instruments (NI) [1]. This study provided a detailed introduction to the encoding mechanism of the approximate lower triangular LDPC, and completed the implementation and verification of FPGA hardware.
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