A data structure for circuit net lists

A data structure for storing and processing electrical circuit net lists is described. The basic data structure is not new, but the version described here is novel in three specific ways. It adds separate structure (arrays) for cell type and I/O-pad-specific information, stores net lists defined in terms of primitive elements or cells as two superimposed symmetric incidence list form directed graphs, and separates primitive element input and output lists to follow signal flow traversal. The focus is on computer-program-level implementation details and on various practical problems arising in circuit net-list processing. The structure's construction cost and algorithmic efficiency are discussed.<>