采用0.18µm CMOS技术提高5 GHz E类功率放大器的功率增益效率的方法

IF 1 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC Iet Circuits Devices & Systems Pub Date : 2023-10-23 DOI:10.1049/2023/5586912

Hemad Heidari Jobaneh

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引用次数: 0

摘要

提出了一种提高E类功率放大器功率附加效率(PAE)的新方法。该放大器工作在5ghz频率，利用电抗补偿技术最大限度地提高工作频率下的带宽。驱动级产生半波整流正弦波或半波整流锯齿波。通过应用每一个波，测试了PA的性能，达到了PAE = 70%和PAE = 50%。另外，在直流电压为1.8 V时，PA的输出功率约为26 dBm。采用先进的设计系统和TSMC 0.18µm CMOS工艺进行仿真。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An Approach to Increase Power-Added Efficiency in a 5 GHz Class E Power Amplifier in 0.18 µm CMOS Technology

A new approach to increasing the power-added efficiency (PAE) of a class E power amplifier (PA) is proposed in this paper. The PA operates at a 5 GHz frequency and a reactance compensation technique is utilized to maximize the bandwidth at the operating frequency. The driver stage creates either a half-wave rectified sine wave or a half-wave rectified sawtooth wave. By applying each one of the waves, the performance of the PA is examined and PAE = 70% and PAE = 50% is achieved. Plus, the output power of the PA is about 26 dBm when the DC voltage supply is 1.8 V. Advanced design system and TSMC 0.18 µm CMOS process are utilized to carry on the simulation.

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来源期刊

Iet Circuits Devices & Systems 工程技术-工程：电子与电气

CiteScore

3.80

自引率

7.70%

发文量

审稿时长

3 months

期刊介绍： IET Circuits, Devices & Systems covers the following topics: Circuit theory and design, circuit analysis and simulation, computer aided design Filters (analogue and switched capacitor) Circuit implementations, cells and architectures for integration including VLSI Testability, fault tolerant design, minimisation of circuits and CAD for VLSI Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs Device and process characterisation, device parameter extraction schemes Mathematics of circuits and systems theory Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers