{"title":"一个具有高线性输入缓冲器的12位2.32 GS/s流水线/SAR混合ADC","authors":"Xuehao Guo, Zhiyang Li, Hao Fang, Zelin Jia, Fuli Tian, Chunyi Song, Zhiwei Xu","doi":"10.1587/elex.20.20230369","DOIUrl":null,"url":null,"abstract":"This paper presents a 12-bit 2.32 GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-to-digital converter (ADC) implemented in 28 nm CMOS. To achieve high-linearity at several GS/s, a pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR hybrid architecture with dual-channel sampling multiplying digital-to-analog converter (MDAC) and one shared flash sub-ADC is used exploiting a simple calibration. The ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 55.68dB and a spurious-free-dynamic-range (SFDR) of 72.18dB at 1125MHz input and consumes 175 mW.","PeriodicalId":50387,"journal":{"name":"Ieice Electronics Express","volume":null,"pages":null},"PeriodicalIF":0.8000,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 12-bit 2.32 GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer\",\"authors\":\"Xuehao Guo, Zhiyang Li, Hao Fang, Zelin Jia, Fuli Tian, Chunyi Song, Zhiwei Xu\",\"doi\":\"10.1587/elex.20.20230369\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 12-bit 2.32 GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-to-digital converter (ADC) implemented in 28 nm CMOS. To achieve high-linearity at several GS/s, a pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR hybrid architecture with dual-channel sampling multiplying digital-to-analog converter (MDAC) and one shared flash sub-ADC is used exploiting a simple calibration. The ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 55.68dB and a spurious-free-dynamic-range (SFDR) of 72.18dB at 1125MHz input and consumes 175 mW.\",\"PeriodicalId\":50387,\"journal\":{\"name\":\"Ieice Electronics Express\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.8000,\"publicationDate\":\"2023-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Ieice Electronics Express\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1587/elex.20.20230369\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Ieice Electronics Express","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1587/elex.20.20230369","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 12-bit 2.32 GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer
This paper presents a 12-bit 2.32 GS/s time-interleaved pipelined/successive-approximation register (SAR) hybrid analog-to-digital converter (ADC) implemented in 28 nm CMOS. To achieve high-linearity at several GS/s, a pseudo-differential push-pull input buffer with floating-body technique is proposed. A pipelined/SAR hybrid architecture with dual-channel sampling multiplying digital-to-analog converter (MDAC) and one shared flash sub-ADC is used exploiting a simple calibration. The ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 55.68dB and a spurious-free-dynamic-range (SFDR) of 72.18dB at 1125MHz input and consumes 175 mW.
期刊介绍:
An aim of ELEX is rapid publication of original, peer-reviewed short papers that treat the field of modern electronics and electrical engineering. The boundaries of acceptable fields are not strictly delimited and they are flexibly varied to reflect trends of the fields. The scope of ELEX has mainly been focused on device and circuit technologies. Current appropriate topics include:
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