Low working loss Si/4H–SiC heterojunction MOSFET with analysis of the gate-controlled tunneling effect

A silicon (Si)/silicon carbide (4H–SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H–SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H–SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_G) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive V_G can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 ​V), the specific on-state resistance (R_ON-SP) of HDT-MOS is reduced by 0.77 ​mΩ‧cm² compared with that of DT-MOS. The gate-to-drain charge (Q_GD) and switching loss of HDT-MOS are 52.14 ​% and 22.59 ​% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_GP) and the corresponding smaller variation (ΔV_GP). The figure of merit (Q_GD ​× ​R_ON-SP) of HDT-MOS decreases by 61.25 ​%. Moreover, the heterointerface charges can reduce R_ON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.