基于变压器模型的一种硬件友好的平铺奇异值分解矩阵乘法

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-10-13 DOI:10.1109/LCA.2023.3323482
Hailong Li;Jaewan Choi;Yongsuk Kwon;Jung Ho Ahn
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引用次数: 0

摘要

基于变压器的模型已经成为许多最先进的自然语言处理(NLP)任务的支柱,包括大型语言模型。矩阵乘法是基于transformer的模型中的一个基本操作,它占用了大部分的执行时间。虽然奇异值分解(SVD)可以通过减少秩大小减少计算量和内存占用来加速该操作,但由于在保留重要信息方面存在挑战,它会导致模型质量下降。此外,这种方法不能有效地利用现代gpu的资源。在本文中,我们提出了一种硬件友好的方法:基于平块奇异值分解(TSVD)的矩阵乘法。TSVD将矩阵划分为多个块,并使用奇异值分解对每个块进行矩阵分解。通过将过程分解成更小的区域,TSVD减轻了重要数据的丢失。我们将TSVD分解的矩阵用于矩阵乘法,与SVD方法相比,我们的基于TSVD的矩阵乘法(TSVD- matl)方法在gpu上表现出更高的效率,特别是对于小问题规模或具有高瘦形状的矩阵。这是因为TSVD-matmul更有效地利用了GPU资源。因此,与SVD方法相比,TSVD-matmul在压缩比为2到8的情况下实现了1.03到3.24倍的加速。当部署到GPT-2时,TSVD不仅在E2E NLG任务上进行了全面微调,而且在2到8压缩比下实现了1.06到1.24倍的加速,同时将精度提高了1.5 BLEU分数。
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A Hardware-Friendly Tiled Singular-Value Decomposition-Based Matrix Multiplication for Transformer-Based Models
Transformer-based models have become the backbone of numerous state-of-the-art natural language processing (NLP) tasks, including large language models. Matrix multiplication, a fundamental operation in the Transformer-based models, accounts for most of the execution time. While singular value decomposition (SVD) can accelerate this operation by reducing the amount of computation and memory footprints through rank size reduction, it leads to degraded model quality due to challenges in preserving important information. Moreover, this method does not effectively utilize the resources of modern GPUs. In this paper, we propose a hardware-friendly approach: matrix multiplication based on tiled singular value decomposition (TSVD). TSVD divides a matrix into multiple tiles and performs matrix factorization on each tile using SVD. By breaking down the process into smaller regions, TSVD mitigates the loss of important data. We apply the matrices decomposed by TSVD for matrix multiplication, and our TSVD-based matrix multiplication (TSVD-matmul) leverages GPU resources more efficiently compared to the SVD approach. As a result, TSVD-matmul achieved a speedup of 1.03× to 3.24× compared to the SVD approach at compression ratios ranging from 2 to 8. When deployed to GPT-2, TSVD not only performs competitively with a full fine-tuning on the E2E NLG task but also achieves a speedup of 1.06× to 1.24× at 2 to 8 compression ratios while increasing accuracy by up to 1.5 BLEU score.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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