Branden Long, Yang Su, Yunfei Wang, Christopher Morgan, Md Faisal Kabir, Ramya Padmanaban, Weston Hearne, Tad Daniel
{"title":"用于逻辑单元操作测试的纳米探测","authors":"Branden Long, Yang Su, Yunfei Wang, Christopher Morgan, Md Faisal Kabir, Ramya Padmanaban, Weston Hearne, Tad Daniel","doi":"10.31399/asm.cp.istfa2023p0420","DOIUrl":null,"url":null,"abstract":"Abstract We have identified a method for nanoprobing CMOS circuits at MHz frequencies using the same hardware already used for single transistor pulsing applications. In this paper we show example responses and failure isolation examples for both sequential and combinational logic cells and discuss the test setup and sample prep that were used to successfully collect the responses.","PeriodicalId":20443,"journal":{"name":"Proceedings","volume":"98 21","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Nanoprobing for Logical Cell Operational Tests\",\"authors\":\"Branden Long, Yang Su, Yunfei Wang, Christopher Morgan, Md Faisal Kabir, Ramya Padmanaban, Weston Hearne, Tad Daniel\",\"doi\":\"10.31399/asm.cp.istfa2023p0420\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Abstract We have identified a method for nanoprobing CMOS circuits at MHz frequencies using the same hardware already used for single transistor pulsing applications. In this paper we show example responses and failure isolation examples for both sequential and combinational logic cells and discuss the test setup and sample prep that were used to successfully collect the responses.\",\"PeriodicalId\":20443,\"journal\":{\"name\":\"Proceedings\",\"volume\":\"98 21\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-11-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.31399/asm.cp.istfa2023p0420\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.31399/asm.cp.istfa2023p0420","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Abstract We have identified a method for nanoprobing CMOS circuits at MHz frequencies using the same hardware already used for single transistor pulsing applications. In this paper we show example responses and failure isolation examples for both sequential and combinational logic cells and discuss the test setup and sample prep that were used to successfully collect the responses.
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