{"title":"高性能图像去噪滤波器的 FPGA 实现","authors":"Nanduri Sambamurthy, Maddu Kamaraju","doi":"10.1007/s10470-023-02208-1","DOIUrl":null,"url":null,"abstract":"<div><p>This paper presents the high performance based one dimension image filter. Image convolution has been widely used in applications followed by image de-nosing filters, feature extraction and computer vision. Realization of two dimensional(2D) convolution based image filter requires massive computational requirements. FPGA based 2D image filter implementation is one of the most challenging task, more computationally exhaustive due to requirement of large number of multiplications and addition operations. The 2D-filter implementation requires extra memory bandwidth for eliminating Gaussian noise. The proposed one dimension (1D) image filter technique reduces the memory access rate by using pixel reuse. Therefore, it improves the performance as well as flexibility. The novelty of the proposed image de-noising filter is hardware reusability, pixels reuse mechanism in accordance with intermediate data shared for consecutive Multiply and Accumulate (MAC) operations. The optimized Reconfigurable Common Subexpression Elimination (RCSE) based MAC diminishes the area in terms of number of multiplications and adder operations of the filter. The 1D-filter approach uses less number of clock cycles and eliminates the data dependencies among neighborhood pixels. In comparison of state-of the art MAC structures, the proposed latency-hiding MAC design achieves optimal delay of 3.396 ns. An evaluation results show that, the design can achieve 9 times better performance and reduces the 40% of area. The power dissipation of the proposed 1D convolution based image filter architecture is 158mw.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2000,"publicationDate":"2023-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://link.springer.com/content/pdf/10.1007/s10470-023-02208-1.pdf","citationCount":"0","resultStr":"{\"title\":\"FPGA implementation of high performance image de-noising filter\",\"authors\":\"Nanduri Sambamurthy, Maddu Kamaraju\",\"doi\":\"10.1007/s10470-023-02208-1\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This paper presents the high performance based one dimension image filter. Image convolution has been widely used in applications followed by image de-nosing filters, feature extraction and computer vision. Realization of two dimensional(2D) convolution based image filter requires massive computational requirements. FPGA based 2D image filter implementation is one of the most challenging task, more computationally exhaustive due to requirement of large number of multiplications and addition operations. The 2D-filter implementation requires extra memory bandwidth for eliminating Gaussian noise. The proposed one dimension (1D) image filter technique reduces the memory access rate by using pixel reuse. Therefore, it improves the performance as well as flexibility. The novelty of the proposed image de-noising filter is hardware reusability, pixels reuse mechanism in accordance with intermediate data shared for consecutive Multiply and Accumulate (MAC) operations. The optimized Reconfigurable Common Subexpression Elimination (RCSE) based MAC diminishes the area in terms of number of multiplications and adder operations of the filter. The 1D-filter approach uses less number of clock cycles and eliminates the data dependencies among neighborhood pixels. In comparison of state-of the art MAC structures, the proposed latency-hiding MAC design achieves optimal delay of 3.396 ns. An evaluation results show that, the design can achieve 9 times better performance and reduces the 40% of area. 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引用次数: 0
摘要
本文介绍了基于高性能的一维图像滤波器。图像卷积已被广泛应用于图像去噪滤波器、特征提取和计算机视觉等领域。实现基于卷积的二维(2D)图像滤波器需要大量的计算要求。基于 FPGA 的二维图像滤波器的实现是最具挑战性的任务之一,由于需要大量的乘法和加法运算,因此计算量更大。二维滤波器的实现需要额外的内存带宽来消除高斯噪声。所提出的一维(1D)图像滤波技术通过像素重用降低了内存访问率。因此,它提高了性能和灵活性。所提出的图像去噪滤波器的新颖之处在于硬件的可重用性,像素重用机制与连续乘法和累加(MAC)操作共享的中间数据相一致。基于可重构公共子表达消除(RCSE)的优化 MAC 减少了滤波器乘法和加法运算的面积。一维滤波器方法使用的时钟周期更少,并消除了邻近像素之间的数据依赖性。与最先进的 MAC 结构相比,所提出的延迟隐藏 MAC 设计实现了 3.396 ns 的最佳延迟。评估结果表明,该设计的性能提高了 9 倍,面积减少了 40%。所提出的基于一维卷积的图像滤波器架构的功耗为 158mw。
FPGA implementation of high performance image de-noising filter
This paper presents the high performance based one dimension image filter. Image convolution has been widely used in applications followed by image de-nosing filters, feature extraction and computer vision. Realization of two dimensional(2D) convolution based image filter requires massive computational requirements. FPGA based 2D image filter implementation is one of the most challenging task, more computationally exhaustive due to requirement of large number of multiplications and addition operations. The 2D-filter implementation requires extra memory bandwidth for eliminating Gaussian noise. The proposed one dimension (1D) image filter technique reduces the memory access rate by using pixel reuse. Therefore, it improves the performance as well as flexibility. The novelty of the proposed image de-noising filter is hardware reusability, pixels reuse mechanism in accordance with intermediate data shared for consecutive Multiply and Accumulate (MAC) operations. The optimized Reconfigurable Common Subexpression Elimination (RCSE) based MAC diminishes the area in terms of number of multiplications and adder operations of the filter. The 1D-filter approach uses less number of clock cycles and eliminates the data dependencies among neighborhood pixels. In comparison of state-of the art MAC structures, the proposed latency-hiding MAC design achieves optimal delay of 3.396 ns. An evaluation results show that, the design can achieve 9 times better performance and reduces the 40% of area. The power dissipation of the proposed 1D convolution based image filter architecture is 158mw.
期刊介绍:
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.