针对故障注入攻击的 RISC-V 微体系结构实验评估

IF 1.9 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Microprocessors and Microsystems Pub Date : 2023-12-20 DOI:10.1016/j.micpro.2023.104991
Maryam Esmaeilian, Hakem Beitollahi
{"title":"针对故障注入攻击的 RISC-V 微体系结构实验评估","authors":"Maryam Esmaeilian,&nbsp;Hakem Beitollahi","doi":"10.1016/j.micpro.2023.104991","DOIUrl":null,"url":null,"abstract":"<div><p><span>Today, the use of embedded processors is increasing dramatically and they are used in all aspects from our daily life to security applications. Physical access to hardware has made the hardware security a major concern. Hardware attacks compromise the hardware security by physically accessing target devices. Among the available techniques for hardware attacks, Fault Injection<span> Attacks (FIAs), such as clock glitching, are one of the most harmful types of non-invasive attacks that can disrupt the operation of an embedded system. Thus, it will be important and fundamental to evaluate </span></span>embedded software<span> programs before using them in critical applications and check their vulnerability against fault injection attacks. However, it is often difficult for software developers to assess vulnerabilities. In this paper, an easy-to-use platform is presented to facilitate the process of evaluating the vulnerability of programs running on embedded processors against clock glitching attacks. Our experimental results show the vulnerability window of RISC-V micro-architecture for different high-level C-functions. The results of this research can help the developers of embedded systems that are used in security applications to evaluate their system against clock glitching attacks with the least cost in a short time.</span></p></div>","PeriodicalId":49815,"journal":{"name":"Microprocessors and Microsystems","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Experimental evaluation of RISC-V micro-architecture against fault injection attack\",\"authors\":\"Maryam Esmaeilian,&nbsp;Hakem Beitollahi\",\"doi\":\"10.1016/j.micpro.2023.104991\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p><span>Today, the use of embedded processors is increasing dramatically and they are used in all aspects from our daily life to security applications. Physical access to hardware has made the hardware security a major concern. Hardware attacks compromise the hardware security by physically accessing target devices. Among the available techniques for hardware attacks, Fault Injection<span> Attacks (FIAs), such as clock glitching, are one of the most harmful types of non-invasive attacks that can disrupt the operation of an embedded system. Thus, it will be important and fundamental to evaluate </span></span>embedded software<span> programs before using them in critical applications and check their vulnerability against fault injection attacks. However, it is often difficult for software developers to assess vulnerabilities. In this paper, an easy-to-use platform is presented to facilitate the process of evaluating the vulnerability of programs running on embedded processors against clock glitching attacks. Our experimental results show the vulnerability window of RISC-V micro-architecture for different high-level C-functions. The results of this research can help the developers of embedded systems that are used in security applications to evaluate their system against clock glitching attacks with the least cost in a short time.</span></p></div>\",\"PeriodicalId\":49815,\"journal\":{\"name\":\"Microprocessors and Microsystems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2023-12-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microprocessors and Microsystems\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0141933123002363\",\"RegionNum\":4,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microprocessors and Microsystems","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0141933123002363","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

摘要

如今,嵌入式处理器的使用正在急剧增加,从我们的日常生活到安全应用的方方面面都在使用它们。对硬件的物理访问使硬件安全成为人们关注的焦点。硬件攻击通过物理访问目标设备来破坏硬件安全。在现有的硬件攻击技术中,故障注入攻击(FIA)(如时钟闪烁)是危害最大的非侵入式攻击类型之一,可破坏嵌入式系统的运行。因此,在关键应用中使用嵌入式软件程序之前,对其进行评估并检查其在故障注入攻击方面的脆弱性是非常重要和基本的。然而,软件开发人员往往很难对漏洞进行评估。本文介绍了一个易于使用的平台,以方便评估在嵌入式处理器上运行的程序对时钟闪烁攻击的脆弱性。我们的实验结果显示了 RISC-V 微体系结构针对不同高级 C 函数的漏洞窗口。这项研究成果可以帮助安全应用领域的嵌入式系统开发人员在短时间内以最低成本评估其系统针对时钟闪烁攻击的脆弱性。
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Experimental evaluation of RISC-V micro-architecture against fault injection attack

Today, the use of embedded processors is increasing dramatically and they are used in all aspects from our daily life to security applications. Physical access to hardware has made the hardware security a major concern. Hardware attacks compromise the hardware security by physically accessing target devices. Among the available techniques for hardware attacks, Fault Injection Attacks (FIAs), such as clock glitching, are one of the most harmful types of non-invasive attacks that can disrupt the operation of an embedded system. Thus, it will be important and fundamental to evaluate embedded software programs before using them in critical applications and check their vulnerability against fault injection attacks. However, it is often difficult for software developers to assess vulnerabilities. In this paper, an easy-to-use platform is presented to facilitate the process of evaluating the vulnerability of programs running on embedded processors against clock glitching attacks. Our experimental results show the vulnerability window of RISC-V micro-architecture for different high-level C-functions. The results of this research can help the developers of embedded systems that are used in security applications to evaluate their system against clock glitching attacks with the least cost in a short time.

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来源期刊
Microprocessors and Microsystems
Microprocessors and Microsystems 工程技术-工程:电子与电气
CiteScore
6.90
自引率
3.80%
发文量
204
审稿时长
172 days
期刊介绍: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) is a journal covering all design and architectural aspects related to embedded systems hardware. This includes different embedded system hardware platforms ranging from custom hardware via reconfigurable systems and application specific processors to general purpose embedded processors. Special emphasis is put on novel complex embedded architectures, such as systems on chip (SoC), systems on a programmable/reconfigurable chip (SoPC) and multi-processor systems on a chip (MPSoC), as well as, their memory and communication methods and structures, such as network-on-chip (NoC). Design automation of such systems including methodologies, techniques, flows and tools for their design, as well as, novel designs of hardware components fall within the scope of this journal. Novel cyber-physical applications that use embedded systems are also central in this journal. While software is not in the main focus of this journal, methods of hardware/software co-design, as well as, application restructuring and mapping to embedded hardware platforms, that consider interplay between software and hardware components with emphasis on hardware, are also in the journal scope.
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