Design a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency and high-speed

In this research work, a novel full adder (FA) circuit is designed based on a hybrid full-swing logic with 20 transistors. The 20-transistor hybrid full-swing adder (HFSA) circuit is designed and measured based on a 12-transistor XOR–XNOR circuit, which can efficiently use chip area and power dissipation. We developed a novel 12-transistor XOR–XNOR circuit that provides glitch-free full-swing outputs. This circuit integrates 2-to-1 multiplexers, pass transistor logic, and inverters. Due to its minimum power consumption and maximum area efficiency, it is a critical component of hybrid full-swing adder circuits. This research aims to measure the efficiency and practicality of novel and eleven existing methods by considering several factors, including performance and measuring key characteristics. As a result, our novel XOR–XNOR circuit offers superior performance compared to its peers—it has a smaller chip area of 7.35 µm², an average power of 2.44 µW, and a propagation delay (25.88 and 24.87) ps, respectively. The proposed full adder has a smaller chip area of 14.157 µm², an average power consumption of 3.582 µW, and a propagation delay of 72.66 ps. It emphasizes large-scale structures, including 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit full adders, as cascade designs utilizing a novel ripple carry adder. We also used the ADEXL design suite to analyze process corners, voltages, and temperatures, which is essential for ensuring circuit accuracy and reliability through multipoint simulations and Monte Carlo analysis. All circuits can be designed and measured in the ADEXL design suite using Cadence Virtuoso software in GPDK 45nm technology. This research shows that HFSA circuits are suitable gates for electronic component assembly. Centralized high-speed processing systems can benefit from HFSA circuits as an alternative to traditional FA circuits.