The Big Chip: Challenge, model and architecture

As Moore’s Law comes to an end, the implementation of high-performance chips through transistor scaling has become increasingly challenging. To improve performance, increasing the chip area to integrate more transistors has become an essential approach. However, due to restrictions such as the maximum reticle area, cost, and manufacturing yield, the chip’s area cannot be continuously increased, and it encounters what is known as the “area-wall”. In this paper, we provide a detailed analysis of the area-wall and propose a practical solution, the Big Chip, as a novel chip form to continuously improve performance. We introduce a performance model for evaluating Big Chip and discuss its architecture. Finally, we derive the future development trends of the Big Chip.