开发浮点运算设备

Georgi Luсkij, Oleksandr Dolholenko
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引用次数: 0

摘要

本文展示了一种众所周知的多核微处理器内核构建方法,该方法基于数据流图驱动计算模型的应用。这种内核的架构基于耶鲁大学帕特提出的精简指令集级数据流模型的应用。研究对象是基于多核微处理器数据流管理的计算模型。本文介绍了浮点乘法器的开发成果,该乘法器可以动态地重新配置,以处理五种不同格式的浮点操作数,并介绍了一种用于浮点数序列加减法的操作设备的构建方法。在所开发的浮点乘法器电路的基础上,可以实现定点和浮点高速乘法器的各种变体,这些变体可能会在商业上得到应用。通过为每个乘法器段添加内存元件,可以选择构建非常快速的流水线乘法器。该乘法器方案有一个局限性:对于非规范化操作数,指数不进行评估,但浮点运算标准并不要求处理非规范化操作数。在这种情况下,乘法器会将结果打包为无穷大。在多核微处理器框架内执行加减运算时,浮点加法器-减法器的核间操作装置的实现可被视为一种实际解决动态规划任务的新方法。其实施的局限性与实施所需的大量硬件成本有关。为了评估这种复杂性,根据浮点标准,对各种浮点数表示格式的主要模块的位值进行了评估。
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Development of floating point operating devices
The paper shows a well-known approach to the construction of cores in multi-core microprocessors, which is based on the application of a data flow graph-driven calculation model. The architecture of such kernels is based on the application of the reduced instruction set level data flow model proposed by Yale Patt. The object of research is a model of calculations based on data flow management in a multi-core microprocessor. The results of the floating-point multiplier development that can be dynamically reconfigured to handle five different formats of floating-point operands and an approach to the construction of an operating device for addition-subtraction of a sequence of floating-point numbers are presented, for which the law of associativity is fulfilled without additional programming complications. On the basis of the developed circuit of the floating-point multiplier, it is possible to implement various variants of the high-speed multiplier with both fixed and floating points, which may find commercial application. By adding memory elements to each of the multiplier segments, it is possible to get options for building very fast pipeline multipliers. The multiplier scheme has a limitation: the exponent is not evaluated for denormalized operands, but the standard for floating-point arithmetic does not require that denormalized operands be handled. In such cases, the multiplier packs infinity as the result. The implementation of an inter-core operating device of a floating-point adder-subtractor can be considered as a new approach to the practical solution of dynamic planning tasks when performing addition-subtraction operations within the framework of a multi-core microprocessor. The limitations of its implementation are related to the large amount of hardware costs required for implementation. To assess this complexity, an assessment of the value of the bits of its main blocks for various formats of representing floating-point numbers, in accordance with the floating-point standard, was carried out.
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发文量
89
审稿时长
8 weeks
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