Hardware optimized digital down converter for multi-standard radio receiver

This paper presents a novel approach to the reconfigurable digital down converter (DDC) reducing the sampling frequency from 3.64 GHz to 28.4375 MHz on the field-programmable gate array (FPGA) device. The proposed DDC consists of a polyphase mixer and a resampling filter. The polyphase mixer can reduce the high-speed sampling rate signal and generates a complex baseband signal having sufficient noise margin. The resampling filter produces a large decimation factor and improves the filtering quality. The design has been optimized at the sub-component level using very few multiplier blocks, resulting in low power consumption. The sampling rate factors can be dynamically programmed in real-time to increase the flexibility of the design. In addition, truncation is used in each filter stage to protect from overflow errors. Moreover, the design is described in optimum hardware description language to reduce the available resources, without compromising the functionality. Finally, the proposed DDC has been simulated and tested on the Xilinx Kintex-7 FPGA board. According to synthesis results, it is noticed that the proposed design reduces the area and power consumption compared to other existing architectures. In the end, the feasibility of the proposed architecture is tested to certify the system’s validity.