采用 28-nm CMOS、最大线性输入电流为 2.2 mApp 的 85 Gb/s PAM-4 TIA

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Solid-State Circuits Letters Pub Date : 2024-01-09 DOI:10.1109/LSSC.2024.3351683

Shuaizhe Ma;Zhenyu Yin;Nianquan Ran;Yifei Xia;Ruixuan Yang;Chuanhao Yu;Songqin Xu;Binhao Wang;Nan Qi;Bing Zhang;Jingbo Shi;Xiaoyan Gui;Li Geng;Dan Li

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引用次数: 0

摘要

本文介绍了一种具有多毫安最大线性输入电流的 100-Gb/s CMOS PAM-4 互阻抗放大器（TIA）。利用可重构前端 (FE) TIA 和在多种增益模式下同步的连续时间线性均衡器 (CTLE)，提出了一种低噪声高线性度 TIA 架构。该 TIA 采用 28-nm CMOS 技术实现，带宽超过 24 GHz，跨阻增益达到 65 dB，同时显示出 10.4 pA/ $\surd $ Hz 的 acrlong IRN 电流密度。最大线性输入电流达到 2.2 mApp，输出摆幅为 600 mV $_{\rm pp, {\mathrm{ diff}}$ 时，总谐波失真（THD）小于 3%。芯片在 1.4 V 和 1.1 V 电源下的功耗为 56 mW。

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A 85-Gb/s PAM-4 TIA With 2.2-mApp Maximum Linear Input Current in 28-nm CMOS

This letter presents a 100-Gb/s CMOS PAM-4 transimpedance amplifier (TIA) with multimilliampere maximum linear input current. A low-noise high-linearity TIA architecture is proposed, leveraging the reconfigurable front-end (FE) TIA and the continuous time linear equalizer (CTLE) synced at multiple gain modes. Implemented in a 28-nm CMOS technology, the TIA achieves bandwidth of more than 24 GHz with transimpedance gain of 65 dB

$\Omega $

, while showing an acrlong IRN current density of 10.4 pA/

$\surd $

Hz. The maximum linear input current reaches 2.2 mApp and the total harmonic distortion (THD) is less than 3% for an output swing of 600 mV

$_{\rm pp, {\mathrm{ diff}}}$

. The chip consumes power of 56 mW from 1.4 and 1.1-V supply.

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