Design and Analyze the Effect of Hetero Material and Dielectric on TFET with Dual Work Function Engineering

As the size of the field effect transistors is reduced down to nanometers, the performance of the devices is affected by various short-channel effects. To overcome these effects, various novel devices are used. Tunnel Field Effect Transistors (TFET) are novel devices in which the drain current needs to be improved. Gate engineering and III-V compound materials are proposed to improve the ON current and reduce the leakage current along with its ambipolar behaviour. As the MOSFET or FinFET devices are scaled below the nanometer regime, unwanted effects like leakage current play a vital role rather than driving current improvement. Conventional MOS transistors have optimized the leakage current by limiting the sub-threshold swing of 60mv/dec. To overcome this limitation, Tunnel Field Effect Transistors (TFET) is considered as the best alternative device for low power applications. The proposed device structure is designed with a heterojunction hetero dielectric dual material gate Tunnel Field Effect Transistor incorporating various combinations of III-V compound materials such as AlGaAsSb/InGaAs, InGaAs/Ge, InGaAs/InP and SiGe/Si. As in III-V composite materials like AlGaAsSb/InGaAs, the narrower bandgap at the source channel interface helps to improve the electric field across the junction. At the same time, the wider bandgap at the channel drain junction leads to unidirectional current flow, resulting in ambipolar reduction. 2D TCAD simulation is used to obtain the electrical parameters for Hetero junction TFETs and the comparison analysis of different Hetero device structures. Many researchers have introduced different heterostructures, but research papers related to dual material heterostructure TFET performance are not available compared with different III–V compound materials combinations. In this paper, performance analysis of the dual material hetero TFET structure for different III–V compound materials combinations such as AlGaAsSb/InGaAs, InGaAs/Ge, InGaAs/InP and SiGe/Si is investigated. The device's electrical parameters, such as energy band diagram, current density, electric field, drain current, gate capacitance and transconductance, have been simulated and analyzed. Besides, the dual material used in the gate, such as Metal1 (M1) and Metal2 (M2), along with HfO2/SiO2 stacked dielectric, helps improve the gate controllability over the channel and the leakage current reduction. The 2D TCAD simulation is used to analyze the electrical parameters of Hetero junction TFETs. The comparison analysis of different Hetero device structure is shown in this section. All the device simulation is carried out using Fermi Dirac carrier statistics model, Lombardi CVT mobility model, Shockley-Read-Hall recombination model, non-local band to band tunneling model, Drift Diffusion current transport model and band gap narrowing model for higher concentration of electron and hole plasma at drain and source side. The parallel stacked dielectrics Al2O3 and HfO2 are used in the simulation which allows the increased gate capacitance. An ION=10-1A/μm, IOFF = 10-12A/μm at drive voltage 0.5V is obtained for InGaAs/InP layer at the source channel hetero junction TFET, and ION=10-2A/μm, IOFF =10-14A/μm at drive voltage 0.5V is obtained for SiGe/Si layer at the source channel hetero junction TFET. Therefore, the InGaAs/InP and SiGe/Si layer TFET are more suitable for ultra-low power integrated circuits.