A reference sampling ΔΣ subsampling PLL

In this work, a new subsampling PLL is presented which samples the reference signal by the oscillator’s phase and then again by the divided oscillator phase. The operation is robust due to the action of a frequency divider in the loop. Fractional synthesis can also be easily implemented by modifying the loop containing the frequency divider using a $\Delta \Sigma$ modulator. Post-layout simulations are performed in CMOS 90 nm technology with a 1 GHz ring oscillator. Peak-to-peak jitter over 1000 cycles of the free running ring oscillator is 87 ps. It is reduced to 28 ps through the action of the proposed architecture.