针对非易失性铁电电容式交叉排列的动态只需电源的内存计算宏程序与两功率非线性 SAR ADC

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Solid-State Circuits Letters Pub Date : 2024-02-01 DOI:10.1109/LSSC.2024.3361011
Injune Yeo;Wangxin He;Yuan-Chun Luo;Shimeng Yu;Jae-Sun Seo
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引用次数: 0

摘要

使用新兴电阻式非易失性存储器 (NVM) 技术的模拟内存计算 (CIM) 面临着各种挑战,例如静态功耗、电流引起的 IR 下降以及需要多个功耗高的 ADC。在这封信中,我们提出了基于铁电电容阵列 (FCA) 的高能效/高面积效率 CIM 宏,用于电荷域乘法累加操作,从而解决了电阻式非易失性存储器 CIM 所面临的挑战。所提出的 CIM 宏包括将三元输入激活和权重编码为电压,并实现寄生不敏感电荷读出。介绍了一种两功率非线性 SAR ADC,其设计旨在实现高能效和硬件友好性。该模数转换器采用基于输入电压的自适应转换跳转,从而实现了集中输入电平的高精度和稀疏输入电平的粗转换。所提出的基于 FCA 的 CIM 宏采用 180-nm CMOS 工艺,在 CIFAR-10 数据集上实现了 $16/times 8$ 模拟 MAC 操作,能效为 1.75 TOPS/W,分类精度为 90.2%。
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A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array
Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the challenges of resistive NVM CIMs. The proposed CIM macro involves encoding ternary input activations and weights into voltages, and enabling parasitic insensitive charge readout. A power-of-two nonlinear SAR ADC is introduced, designed for energy-efficiency and hardware-friendliness. This ADC employs adaptive conversion skipping based on input voltage, resulting in fine precision for concentrated input levels and coarse conversion for sparse input levels. The proposed FCA-based CIM macro in 180-nm CMOS demonstrates $16\times 8$ analog MAC operation with an energy efficiency of 1.75 TOPS/W and classification accuracy of 90.2% is obtained for the CIFAR-10 dataset.
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来源期刊
IEEE Solid-State Circuits Letters
IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering
CiteScore
4.30
自引率
3.70%
发文量
52
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