{"title":"基于高电压 BCD 工艺的源分段式 LDMOS 结构可提高单次烧毁容限","authors":"Jiang Xu;Zeyu Lei;Chenchen Zhang;Xin Wan;Zhuojun Chen","doi":"10.1109/TDMR.2024.3349621","DOIUrl":null,"url":null,"abstract":"The Lateral Diffused Metal Oxide Semiconductor (LDMOS) is vulnerable to Single-Event Burnout (SEB) effect in the radiation environment, which is challenging for the design of high-voltage integrated circuit (HVIC). In this work, a Source-Segmented LDMOS (SS-LDMOS) structure for SEB hardness is proposed, which can reduce parasitic resistor and enhance hole discharge capacity nearby the source region. Through pulsed-laser experiments, the proposed devices are validated in two different high-voltage Bipolar-CMOS-DMOS (BCD) processes. Compared to conventional LDMOS, the SS-LDMOS can provide an improvement of SEB triggering voltage by 20.7% to 40%, without changing its electrical parameters such as threshold voltage, on-resistance, and breakdown voltage. Besides, the proposed approach has the advantage of zero additional mask, no additional processing step, and compact structure, in comparison with other existing hardness techniques. Therefore, it is promising in HVIC for aerospace applications.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 1","pages":"105-111"},"PeriodicalIF":2.5000,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Source Segmented LDMOS Structure for Improving Single Event Burnout Tolerance Based on High-Voltage BCD Process\",\"authors\":\"Jiang Xu;Zeyu Lei;Chenchen Zhang;Xin Wan;Zhuojun Chen\",\"doi\":\"10.1109/TDMR.2024.3349621\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Lateral Diffused Metal Oxide Semiconductor (LDMOS) is vulnerable to Single-Event Burnout (SEB) effect in the radiation environment, which is challenging for the design of high-voltage integrated circuit (HVIC). In this work, a Source-Segmented LDMOS (SS-LDMOS) structure for SEB hardness is proposed, which can reduce parasitic resistor and enhance hole discharge capacity nearby the source region. Through pulsed-laser experiments, the proposed devices are validated in two different high-voltage Bipolar-CMOS-DMOS (BCD) processes. Compared to conventional LDMOS, the SS-LDMOS can provide an improvement of SEB triggering voltage by 20.7% to 40%, without changing its electrical parameters such as threshold voltage, on-resistance, and breakdown voltage. Besides, the proposed approach has the advantage of zero additional mask, no additional processing step, and compact structure, in comparison with other existing hardness techniques. Therefore, it is promising in HVIC for aerospace applications.\",\"PeriodicalId\":448,\"journal\":{\"name\":\"IEEE Transactions on Device and Materials Reliability\",\"volume\":\"24 1\",\"pages\":\"105-111\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2024-01-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Device and Materials Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10380792/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10380792/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A Source Segmented LDMOS Structure for Improving Single Event Burnout Tolerance Based on High-Voltage BCD Process
The Lateral Diffused Metal Oxide Semiconductor (LDMOS) is vulnerable to Single-Event Burnout (SEB) effect in the radiation environment, which is challenging for the design of high-voltage integrated circuit (HVIC). In this work, a Source-Segmented LDMOS (SS-LDMOS) structure for SEB hardness is proposed, which can reduce parasitic resistor and enhance hole discharge capacity nearby the source region. Through pulsed-laser experiments, the proposed devices are validated in two different high-voltage Bipolar-CMOS-DMOS (BCD) processes. Compared to conventional LDMOS, the SS-LDMOS can provide an improvement of SEB triggering voltage by 20.7% to 40%, without changing its electrical parameters such as threshold voltage, on-resistance, and breakdown voltage. Besides, the proposed approach has the advantage of zero additional mask, no additional processing step, and compact structure, in comparison with other existing hardness techniques. Therefore, it is promising in HVIC for aerospace applications.
期刊介绍：
The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.
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