通过 HLS4ML 实现基于 SoC 的用于 3 通道心电图心律失常分类的一维卷积神经网络

IF 1.7 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Embedded Systems Letters Pub Date : 2024-01-15 DOI:10.1109/LES.2024.3354081
Feroz Ahmad;Saima Zafar
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引用次数: 0

摘要

实时监测一维生物电位,如心电图(ECG),需要有效的特征提取和分类,这是深度学习(DL)算法的优势。通过开源协同设计工作流程设计1-D卷积神经网络(1-D CNN)加速器用于生物电位分类,特别是用于机器学习的高级合成(HLS4ML),与基于gpu或基于云的解决方案相比,具有高性能、低延迟、低功耗、快速上市和成本效益等优势。我们在PYNQ Z2 SoC上使用HLS4ML实现了量化修剪(QP) 1-D CNN模型,通过无缝部署其通过Vivado Accelerator后端生成的软IP核,展示了量化感知训练(QAT)将功耗从1.823 W降低到1.655 W的有效性。我们的方法表明,与基线(B) 1-D CNN模型相比,该方法改善了面积消耗、资源利用率和每秒推断量,加权精度、精密度、召回率和f1评分降低了4%或更少,揭示了实时3通道心电心律失常分类的性能指标和系统效率之间的微妙权衡。
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SoC-Based Implementation of 1-D Convolutional Neural Network for 3-Channel ECG Arrhythmia Classification via HLS4ML
Real-time monitoring of 1-D biopotentials, such as electrocardiograms (ECG), necessitates effective feature extraction and classification, a strength of deep learning (DL) algorithms. Designing 1-D convolutional neural network (1-D CNN) accelerators for biopotential classification via open-source codesign workflows, particularly high-level synthesis for machine learning (HLS4ML), offers advantages over GPU-based or cloud-based solutions, including high performance, low latency, low power consumption, swift time-to-market, and cost-effectiveness. We present an implementation of a quantized-pruned (QP) 1-D CNN model on the PYNQ Z2 SoC using HLS4ML by seamlessly deploying its soft IP core generated via Vivado Accelerator backend, showcasing the efficacy of quantization-aware training (QAT) in reducing power consumption to 1.655 W from 1.823 W. Our approach demonstrates improved area consumption, resource utilization, and inferences per second compared to the baseline (B) 1-D CNN model, with a controlled 4% or less reduction in weighted Accuracy, Precision, Recall, and F1-score, revealing the nuanced tradeoffs between performance metrics and system efficiency for real-time 3-channel ECG Arrhythmia classification.
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来源期刊
IEEE Embedded Systems Letters
IEEE Embedded Systems Letters Engineering-Control and Systems Engineering
CiteScore
3.30
自引率
0.00%
发文量
65
期刊介绍: The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.
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Table of Contents Editorial IEEE Embedded Systems Letters Publication Information ViTSen: Bridging Vision Transformers and Edge Computing With Advanced In/Near-Sensor Processing Methodology for Formal Verification of Hardware Safety Strategies Using SMT
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