利用锥形氧化硅掩模制造尖端顶点小于 5 纳米的高有序硅纳米锥阵列

IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Semiconductor Manufacturing Pub Date : 2024-03-04 DOI:10.1109/TSM.2024.3372521
Aixi Pan;Chenxu Zhu;Zheng Yan;Xiaoli Zhu;Zhongyi Liu;Bo Cui
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引用次数: 0

摘要

鉴于超锐利硅(Si)纳米锥的广泛应用,人们对其制造工艺进行了广泛的研究。然而,这些传统方法在实现均匀性、可控性和成本效益方面存在挑战。本研究提出了一种新方法,通过使用锥形二氧化硅掩模进行反应离子蚀刻(RIE),然后通过热氧化锐化将顶点直径减小到 4 纳米,从而制造出 Si 纳米锥结构。这里的锥形二氧化硅掩膜具有光滑的侧壁,是通过 RIE 和缓冲氧化物蚀刻剂(BOE)蚀刻相结合的方法制作的。氧化物掩模的光刻是通过一种经济有效的(与电子束光刻相比)无掩模对准器系统(MLA)来实现的。随后,使用六氟化硫(SF6)气体和八氟环丁烷(C4F8)气体的非开关伪博世工艺蚀刻硅纳米锥结构,使其平均顶点直径达到 30 纳米。最后,通过热氧化和去除氧化物,这些锥形结构进一步锐化到 4 纳米。
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Fabrication of the Highly Ordered Silicon Nanocone Array With Sub-5 nm Tip Apex by Tapered Silicon Oxide Mask
In view of the wide range of applications for ultra-sharp silicon (Si) nanocones, extensive research has been conducted on their fabrication processes. However, these conventional methods pose challenges in terms of achieving uniformity, controllability, and cost-efficiency. This study presents a novel approach to fabricating Si nanocone structures through reactive ion etching (RIE) using a tapered silicon dioxide mask, followed by thermal oxidation sharpening to reduce the apex diameter to 4 nm. Here the tapered SiO2 mask with a smooth sidewall was created through a combination of RIE and a buffered oxide etchant (BOE) etching. The lithography of the oxide mask is achieved using a cost-effective (compared to electron beam lithography) maskless aligner system (MLA). Subsequently, a non-switching pseudo-Bosch process, employing sulfur hexafluoride (SF6) gas and octafluorocyclobutane (C4F8) gas, is utilized for the etching the Si nanocone structures, resulting in an average apex diameter of 30 nm. Finally, thermal oxidation followed by oxide removal further sharpens these cones to 4 nm.
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来源期刊
IEEE Transactions on Semiconductor Manufacturing
IEEE Transactions on Semiconductor Manufacturing 工程技术-工程:电子与电气
CiteScore
5.20
自引率
11.10%
发文量
101
审稿时长
3.3 months
期刊介绍: The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components, especially very large scale integrated circuits (VLSI). Manufacturing these products requires precision micropatterning, precise control of materials properties, ultraclean work environments, and complex interactions of chemical, physical, electrical and mechanical processes.
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