{"title":"用于心电图记录的超低功耗固定窗口电平转换 ADC。","authors":"Mahdi Ghasemi, Nassim Ravanshad, Hamidreza Rezaee-Dehsorkh","doi":"10.1109/TBCAS.2024.3376642","DOIUrl":null,"url":null,"abstract":"<p><p>In this paper, a novel fixed-window level-crossing analog-to-digital converter (LCADC) is proposed for the ECG monitoring application. The proposed circuit is implemented using fewer comparators and reference levels compared to the conventional structure, which results in a decrease in complexity and occupied silicon area. Also, the power consumption is reduced considerably by decreasing the activity of the comparator. Simulation results show a 5-fold reduction in activity by applying the standard ECG signals to the proposed structure. The proposed circuit is implemented in 0.18 μm CMOS technology using a 0.9 V supply voltage. Measurement results show a 5.9 nW power consumption and a 7.4-bit resolution. The circuit occupies a 0.05846 mm<sup>2</sup> silicon area. A typical level-crossing-based R-peak-detection algorithm is applied to the output samples of the LCADC, which shows the effectiveness of using this type of sampling.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Ultra-Low Power Fixed-Window Level Crossing ADC for ECG Recording.\",\"authors\":\"Mahdi Ghasemi, Nassim Ravanshad, Hamidreza Rezaee-Dehsorkh\",\"doi\":\"10.1109/TBCAS.2024.3376642\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p><p>In this paper, a novel fixed-window level-crossing analog-to-digital converter (LCADC) is proposed for the ECG monitoring application. The proposed circuit is implemented using fewer comparators and reference levels compared to the conventional structure, which results in a decrease in complexity and occupied silicon area. Also, the power consumption is reduced considerably by decreasing the activity of the comparator. Simulation results show a 5-fold reduction in activity by applying the standard ECG signals to the proposed structure. The proposed circuit is implemented in 0.18 μm CMOS technology using a 0.9 V supply voltage. Measurement results show a 5.9 nW power consumption and a 7.4-bit resolution. The circuit occupies a 0.05846 mm<sup>2</sup> silicon area. A typical level-crossing-based R-peak-detection algorithm is applied to the output samples of the LCADC, which shows the effectiveness of using this type of sampling.</p>\",\"PeriodicalId\":94031,\"journal\":{\"name\":\"IEEE transactions on biomedical circuits and systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-03-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE transactions on biomedical circuits and systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TBCAS.2024.3376642\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE transactions on biomedical circuits and systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TBCAS.2024.3376642","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Ultra-Low Power Fixed-Window Level Crossing ADC for ECG Recording.
In this paper, a novel fixed-window level-crossing analog-to-digital converter (LCADC) is proposed for the ECG monitoring application. The proposed circuit is implemented using fewer comparators and reference levels compared to the conventional structure, which results in a decrease in complexity and occupied silicon area. Also, the power consumption is reduced considerably by decreasing the activity of the comparator. Simulation results show a 5-fold reduction in activity by applying the standard ECG signals to the proposed structure. The proposed circuit is implemented in 0.18 μm CMOS technology using a 0.9 V supply voltage. Measurement results show a 5.9 nW power consumption and a 7.4-bit resolution. The circuit occupies a 0.05846 mm2 silicon area. A typical level-crossing-based R-peak-detection algorithm is applied to the output samples of the LCADC, which shows the effectiveness of using this type of sampling.