IEEE transactions on biomedical circuits and systems最新文献

This article presents a direct-digitization analog front end (DD-AFE) with enhanced input-impedance, common-mode rejection ratio (CMRR), and dynamic range (DR) for wearable biopotential (ExG) signal acquisition, especially for small-diameter dry electrodes. The DD-AFE employs a second-order continuous-time delta-sigma modulator (CT-ΔSM) and multiple circuit techniques to support direct-digitization readouts. These include 1) A high input-impedance input feedforward (FF), embedded in a 4-input 4-bit successive approximation register (SAR) quantizer. This allows two integrators to adopt a compact and energy-efficient G_m-C structure, and improves stability and linearity, resulting in a 6.6dB increase in DR, 42dB increase in SQNR at peak input and a unity-gain signal transfer function (STF) with a gain flatness of 0.04%. 2) A fixed-voltage dead-band assisted tri-level current-steering DAC (IDAC). It not only increases the DR and CMRR of the DD-AFE but also eliminates the harmonic distortion induced by tri-level dynamic element matching (DEM). 3) A high-gain two-stage G_m-boosting inverter-based OTA with embedded low-frequency chopping. The former largely improves linearity and CMRR, while the latter mitigates 1/f noise without compromising the input impedance. Fabricated in a 0.18-μm CMOS process, this DD-AFE achieves 6.4GΩ input impedance and 104.5dB CMRR at 50Hz, as well as 90.4dB peak SNDR, 96dB DR, and up to 425mV_PP linear input range.

The paper proposes a low-power Successive Approximation Register (SAR) Analog-to-Digital Conversion (ADC) with dual bypass windows based on non-binary split capacitors. To reduce the power consumption, the bypass windows constituted by the split capacitors can maximize the coverage of biological signals both in the resting state and excited state. When the signal falls within the designated window, unnecessary conversion cycles are skipped. This process is mainly judged and controlled by digital circuits, which is highly robust and does not require calibration. Meanwhile, a low-power dynamic CMOS comparator is proposed, which can effectively reduce the voltage variation of the latch node during the comparator's operation, further reducing power consumption. The proposed SAR ADC, based on a 180nm process, measures a power consumption of 9.68nW at a supply voltage of 0.6V and a sampling rate of 5.21kS/s. The signal-to-noise-and-distortion ratio (SNDR) and the spur-free dynamic range (SFDR) are measured at 57.51dB and 71.68dB, respectively. It also achieves an effective number of bits (ENOB) of 9.26 bits and a Walden figure-of-merit (FoM) of 2.9 fJ/conv.-step. The proposed SAR ADC is also verified by collected electromyogram (EMG), electrocardiogram (ECG), and electroencephalogram (EEG) signals. The average power consumption for quantifying EMG signals is 7.95 nW, providing an attractive solution for low-power SAR ADCs in biomedical applications.

Motion artifacts (MA), common-mode interference (CMI), and varying electrode-tissue impedance (ETI) are the main factors that cause heart rate detection errors in practical wearable ECG acquisition. These problems are further exacerbated in two-electrode based ECG systems. This article presents an ambulatory ECG acquisition ASIC with fully integrated, low power motion artifacts removal (MAR) and heart rate detection, specifically for two-electrode ECG measurement. To alleviate the significant CMI due to the absence of subject bias electrode, this work utilizes an improved common-mode cancellation scheme to suppress CMI up to 40V_pp with dynamic power consumption. To address excessive MA caused by the body movement, a hybrid MAR technique is proposed, where both ETI and DC electrode offset (DEO) signals are incorporated as inputs to the adaptive filter. This approach not only prevents channel saturation in a power-efficient manner, but also accurately extracts MA and suppresses it in real time, thereby ensuring stable ECG outputs and accurate, power-efficient R-peak detection even in the presence of body movements. Fabricated in a standard 180nm CMOS process, the core IA achieves an input referred noise (IRN) of 0.62μV_rms (1-150Hz), an input impedance of 1.9GΩ and a total-CMRR (T-CMRR) of 92dB at 50Hz. In a two-electrode configuration, the ASIC successfully suppresses the MA and obtains a high-quality ECG with well-identified QRS complex, enabling the built-in R-peak detection algorithm to calculate real-time heart rate more accurately and efficiently.

This paper presents the first end-to-end next-generation sequencing (NGS) data analysis accelerator for short-read mapping, haplotype calling, variant calling, and genotyping. It supports both single-end and paired-end short-reads (or reads) and uses the FM-index, a compact index data structure, for exact-match in short-read mapping. For inexact match part of short-read mapping, a dynamic programming array is proposed to determine the mapping results. To reduce the workload of short-read mapping, a rapid similarity calculation is designed. A rescue technique is also adopted to increase the overall sensitivity. In haplotype calling, a parallel k-mer processing engine can construct the de Bruijn graph and assemble the haplotypes. The variant calling step determines variants between a subject and a reference genome sequence with a variant discovery engine. Lastly, genotype likelihood is computed in parallel by a genotype likelihood computing engine, which outputs genotypes of all discovered variants and corresponding Phred-scaled likelihood (PL) values. This work completes end-to-end data analysis for the 50× PrecisionFDA dataset in an average of 28.2 minutes. It achieves a 3-to-59× higher throughput than the existing solutions with higher precision (99.79%) and sensitivity (99.03%). The chip also achieves a 935× higher energy efficiency than the Illumina DRAGEN FPGA acceleration system.