IEEE transactions on biomedical circuits and systems最新文献

This paper presents the design of a high-resolution fully-integrated tactile sensor system, called DERMIS, implemented in a flexible thin-film transistor (TFT) technology for large-area electronic skins. It discusses how an end-to-end design strategy - from the sensor to the readout and to the on-chip feature extraction - enables efficient system reconfiguration to implement a first-of-its-kind and biologically-inspired grasp-state-adaptive tactile sensor. In contrast to existing tactile sensors that only detect slip, the DERMIS system also measures key contact cues, including friction, contact onset/offset, and lift-off onset/offset, enabled by a novel differential capacitive sensorstructure that independently senses shear and normal forces and a co-designed front end that directly extracts both components at the analog domain. Furthermore, due to the analog-based encoding of these grasp-state-dependent contact parameters, the system avoids the use of complex offline slip-extraction algorithms. The per-taxel (tactile pixel) readout consumes a state-of-the-art 72 µW power consumption and occupies 0.36 mm² area while achieving a human-like 2 mN_RMS force resolution at 0.6 mm pitch. This work demonstrates our solution for the first time in a true large-area prototype of 9×4 mm².

The growing demand for continuous physiological monitoring and human-machine interaction in realworld settings calls for wearable platforms that are flexible, low-power, and capable of on-device intelligence. This work presents BioGAP-Ultra, an advanced multimodal biosensing platform that supports synchronized acquisition of diverse electrophysiological and hemodynamic signals such as EEG, EMG, ECG, and PPG while enabling embedded AI processing at state-of-the-art energy efficiency. BioGAP-Ultra is a major extension of our previous BioGAP design aimed at meeting the rapidly growing requirements of wearable biosensing applications. It features (i) increased on-device storage (×2 SRAM, ×4 FLASH), (ii) improved wireless connectivity (supporting up to 1.4 Mbit/s bandwidth, ×4 higher than BioGAP), (iii) enhanced number of signal modalities (from 3 to 5) and analog input channels (×2). Further, it is accompanied by a real-time visualization and analysis software suite that supports the hardware design, providing access to raw data and real-time configurability on a mobile phone. Finally, we demonstrate the system's versatility through integration into various wearable form factors: an EEG-PPG headband consuming 32.8 mW, an EMG sleeve at 26.7 mW, and an ECG-PPG chestband requiring only 9.3 mW for continuous acquisition and streaming, tailored for diverse biosignal applications. To showcase its edge-AI capabilities, we further deploy two representative on device applications: (1) ECG-PPG-based PAT estimation at 8.6 mW, and (2) EMG-ACC-based classification of reach-and grasp motion phases, achieving 79.9 % ± 5.7 % accuracy at 23.6 mW. All hardware and software design files are also released open-source with a permissive license.

This paper proposes a millimeter-sized, high-sensitivity, wide dynamic-range 16-channel electrochemical sensing SoC with integrated thin-film organic electrochemical transistor (OECT), utilizing ultrasonic wireless power and backscatter wireless communication technology. A bidirectional current conveyor and resistor (CC+R) potentiostat with duty-cycle control is introduced to minimize the static current consumption by reducing the duty cycle of the OECT amplification process. Additionally, the programmable gain amplifier's (PGA's) sampling capacitor is repurposed for small current-to-voltage conversion, extending the measurement range with minimal overhead. The system further integrates an active full-wave rectifier with backscatter amplitude modulation, supporting a wide range of received pulse amplitudes, variable time-of-flight (ToF), and tunable ultrasound frequencies. The design is fabricated using a 180 nm CMOS process. Experimental result features a sensing current measurement range of 184 dB, with a minimum current noise of 1.25 pA_rms. The power consumption of the single-channel system is 16.3 $μ$W. The design was validated for the detection of inflammatory factors, achieving a limit of detection (LoD) as low as 0.1 pM and the linearity with R² greater than 0.95.

We present a 43 $μ$m × 269 μm tetherless neural recording microsystem in which the CMOS bulk is forward biased to utilize silicon junctions as a photovoltaic source. Our microsystem, forward-bulk microscale optoelectronic tetherless electrode (FB-MOTE), can operate with as low as 0.2 $μ$A at 0.317 V and can withstand light intensity up to 1200 $μ$W/mm², and is power-adaptive: the higher available power increases the system bandwidth while maintaining the input-referred integrated noise. To balance between adaptability and stability, we have designed our amplifier to take up most of the additional power, hence acting like a regulator, while the other circuit blocks are PTAT-biased to remain relatively stable across available power levels. The amplified neural signals are pulse position modulated (PPM) and optically transmitted through an AlGaAs microscale light emitting diode ($μ$LED) for its information per-photon efficiency, where the $μ$LED driver is designed to maximize the emission-to-area ratio. Finally, we discuss various light-induced effects observed in measurements and introduce a simulation methodology to account for such effects and its limitations. Our forward-bulk CMOS microsystem provides an approach that can effectively harness and account for the available light in optoelectronic systems design.

We present a 6.78-MHz wireless, mode-convertible single-stage resonant charger (SSRC) that provides constant current/constant voltage charging in an extended coupling range for implantable biomedical devices. To extend the charging range in a wireless inductive link for reliable and seamless power transfer, it automatically switches between normal and resonant modes (NM and RM) by sensing current variation induced from the frequency splitting phenomenon, thereby achieving an extended charging distance up to 104.34 %. In addition, the proposed charger limits the maximum current to avoid excessive charging, that potentially degrades the battery's health. The prototype SSRC has been fabricated using a 180 nm bipolar/CMOS/DMOS high voltage process with an active area of 0.575 mm2. The performance of the fabricated chip has been characterized on benchtop and ex vivo using a custom-designed 3-D printed fixture. The measurement results verified efficient power delivery to batteries while extending the charging distance from 23 mm to 47 mm in air and a 20-mm-thick pork slice without over-current issues. The measured peak power conversion efficiencies were 89.42 and 76.6 % in the NM and RM, respectively.

This paper introduces a capacitively coupled analog front-end featuring an adjustable high-pass cutoff frequency range of 7mHz to 6.29 Hz. The DC operating point for the input differential pair is set by the dynamic equilibrium of the direct tunneling (DT) current. An output DC-servo loop (O-DSL), utilizing a duty-cycled operational transconductance amplifier (DC-OTA) together with a digital-assistant transconductance amplifier (DA-OTA), is designed at the main amplifier's output nodes. By employing DC-OTA techniques in the O-DSL, an equivalent transconductance as low as 0.18 pA/V has been achieved, enabling the front-end to reach a 7mHz high-pass cutoff frequency with a 6 pF on-chip integrating capacitor. A DA-OTA technique is used to widen the compensation range for low frequency interference. Additionally, a positive feedback capacitor in conjunction with a dual loop control mechanism is applied to enhance input impedance to 5.2GΩ at 50 Hz within 30 ms calibration time. The front-end is fabricated in a standard 180 nm CMOS process, with a total current consumption of 3.01 μA and 6.37NEF.

Cardiovascular diseases (CVDs) are among the leading causes of mortality. Traditional diagnostic methods require hospital visits and professional medical personnel, but the timely detection of cardiac conditions can significantly improve survival rates. Therefore, wearable devices with edge-computing capabilities for real-time cardiovascular diagnosis are highly important. Heart sounds provide valuable information on valve closure; however, variations in heart rhythm or heart valve diseases (HVDs) can complicate the identification of affected valves and the interpretation of heart sound origins. Additionally, different disease classifications require distinct model architectures, posing significant challenges for implementation on wearable devices. This study addresses these challenges through three key contributions: an ECG-gating PCG algorithm, improved classification algorithms for arrhythmia and valvular heart disease, and a systolic array-based accelerator with an application-specific instruction-set processor (ASIP) capable of performing inference on multiple models. The algorithms achieve 97.8% and 99.3% accuracy on the MIT-BIH and heart murmur databases, respectively, with hardware quantization errors below 0.5%. The accelerator is fabricated in TSMC 180 nm CMOS technology, achieving an operating power of 414 $μ$W at 1 MHz. The execution times for arrhythmia and valvular heart disease classification are 7.2 ms and 21 ms, respectively, and the energy efficiency normalized to 40 nm is 395.3 GOPS/W. These show that this system can effectively solve the classification of arrhythmia and heart valve diseases.

The therapeutic efficacy of closed-loop neuro-modulation is critically undermined by stimulation artifacts that create a prolonged amplifier "blind period", obscuring neural biomarkers. While state-of-the-art solutions mitigate this by adding complexity around the amplifier-such as active reset, blanking, or digital cancellation-they introduce trade-offs like data loss or computational overhead. In a distinct departure from these approaches, this paper solves the problem at its root by introducing a state-aware feedback element: a self-adaptive pseudo-resistor (A-PR). The A-PR architecture integrates two key innovations: an adaptive Floating Power Supply (FPS) that senses DC errors and autonomously collapses the feedback resistance for rapid recovery, and a process-insensitive Self-Biased Current Source (SBCS) that ensures robust, uniform performance against PVT variations. A complete neural recording front-end featuring the A-PR was fabricated in a 40-nm CMOS process. Measurement results validate the core claims, demonstrating a sub-3-ms recovery time from a 1-V artifact, an input-referred noise of 5.23 $μ$V_rms, and a tunable high-pass corner, all while consuming only 2.3 $μ$W and occupying 0.015 mm^². By eliminating the trade-off between fast recovery and high fidelity, the A-PR provides a scalable, low-power solution for next-generation, high-resolution closed-loop neural interfaces.

Next-generation neurorehabilitation implants demand high-channel-count closed-loop systems with ultra-low area and ultra-low-power readout and classification. This is essential in applications such as multi-type epileptic seizure detection, brain machine interfaces or brain-to-text conversion. Although recent designs achieve compactness and low power, they often cannot record neural signals during stimulation due to large, saturating artifacts. Conversely, artifact-tolerant solutions typically incur excessive area and power overhead to avoid saturation. We introduce a paradigm shift: enabling an ultra-compact, artifact-tolerant readout frontend by permitting brief saturation during stimulation pulses and applying backend interpolation to reconstruct the signals. High-fidelity neural features can thus be extracted with minimal error. To minimize the readout area footprint and to facilitate the routing from many electrodes, we reuse the whole frontend to read-out 64 inputs in a time-multiplexed fashion. Implemented in a 40nm CMOS process, our chip leverages the first published secondorder fully time-based incremental analog-to-digital converter, achieving a state-of-the-art 290-$μ$m²/ch area occupation and only 610-nW/ch of power consumption. The proposed hybrid electrode offset compensation further minimizes the area overhead without significantly compromising the noise or common-mode/power rejection across the full cancellation range. Artifact tolerance is validated in saline using an external stimulator chip. We demonstrate that the error on a broad set of features extracted from interpolated local-field-potential data remains below ±10%, even under harsh stimulation conditions.