Pub Date : 2026-02-09DOI: 10.1109/TBCAS.2026.3662427
Lun Lu, Ao Xu, Youpeng Wu, Mingxin Deng, Yi Sun, Zhiwei Li, Yinan Wang, Qingjiang Li
The prediction of epileptic seizures can significantly improve patients' quality of life by enabling timely preventive interventions. However, realizing automated real-time prediction on edge hardware remains challenging due to high computational complexity, inefficient temporal signal processing, and the von Neumann bottleneck. In this work, we propose a memristor-based multi-stage reservoir computing architecture that jointly addresses algorithmic and hardware limitations. Volatile memristors are employed in reservoir modules to perform nonlinear temporal feature extraction, avoiding error accumulation issues commonly observed in recurrent neural networks. Non-volatile memristor crossbar arrays are further integrated to implement in-memory analog multiply-accumulate operations, significantly reducing data movement and improving hardware efficiency. Owing to the proposed multi-stage structure, high prediction accuracy is achieved with only 1,700 trainable parameters. Moreover, comprehensive hardware-aware evaluations are conducted, including input noise injection, device-to-device and cycle-to cycle variations to assess robustness against memristor non-idealities. Results demonstrate that the proposed system achieves over 97% accuracy in simulation and exceeds 95% accuracy in hardware experiments, while maintaining stable performance under substantial noise, making it a promising low-power solution for real-time seizure prediction on edge platforms.
{"title":"Memristive Reservoir Computing Circuit for Real-Time Prediction of Epilepsy.","authors":"Lun Lu, Ao Xu, Youpeng Wu, Mingxin Deng, Yi Sun, Zhiwei Li, Yinan Wang, Qingjiang Li","doi":"10.1109/TBCAS.2026.3662427","DOIUrl":"https://doi.org/10.1109/TBCAS.2026.3662427","url":null,"abstract":"<p><p>The prediction of epileptic seizures can significantly improve patients' quality of life by enabling timely preventive interventions. However, realizing automated real-time prediction on edge hardware remains challenging due to high computational complexity, inefficient temporal signal processing, and the von Neumann bottleneck. In this work, we propose a memristor-based multi-stage reservoir computing architecture that jointly addresses algorithmic and hardware limitations. Volatile memristors are employed in reservoir modules to perform nonlinear temporal feature extraction, avoiding error accumulation issues commonly observed in recurrent neural networks. Non-volatile memristor crossbar arrays are further integrated to implement in-memory analog multiply-accumulate operations, significantly reducing data movement and improving hardware efficiency. Owing to the proposed multi-stage structure, high prediction accuracy is achieved with only 1,700 trainable parameters. Moreover, comprehensive hardware-aware evaluations are conducted, including input noise injection, device-to-device and cycle-to cycle variations to assess robustness against memristor non-idealities. Results demonstrate that the proposed system achieves over 97% accuracy in simulation and exceeds 95% accuracy in hardware experiments, while maintaining stable performance under substantial noise, making it a promising low-power solution for real-time seizure prediction on edge platforms.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146151560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-28DOI: 10.1109/TBCAS.2025.3639842
{"title":"IEEE Transactions on Biomedical Circuits and Systems Publication Information","authors":"","doi":"10.1109/TBCAS.2025.3639842","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3639842","url":null,"abstract":"","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 1","pages":"C2-C2"},"PeriodicalIF":4.9,"publicationDate":"2026-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11367245","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146057660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-28DOI: 10.1109/TBCAS.2026.3654281
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TBCAS.2026.3654281","DOIUrl":"https://doi.org/10.1109/TBCAS.2026.3654281","url":null,"abstract":"","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 1","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2026-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11367140","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146057661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The detection of arrhythmias is crucial in monitoring cardiac health. However, electrocardiogram (ECG) signals obtained from wearable devices are often compromised by noise, including electrode motion artifacts, baseline wander, and muscle artifacts. This paper addresses these challenges by proposing a highly robust cardiac health monitoring processor featuring a cascaded triple-adaptive QRS detector and medically driven feature-fusion hybrid neural networks (HNN) for arrhythmia classification. The QRS detector uses a self-adaptive triplethreshold mechanism that dynamically correlates duration, RR interval, and error correction thresholds, allowing it to accurately identify QRS complex features in noisy signals, facilitated by event-driven sampling. The HNN arrhythmia classifier combines long short-term memory (LSTM) and artificial neural network (ANN) architectures with three medically driven pathological feature fusion, achieving improved computational efficiency. The prototype is fabricated using the 65-nm CMOS process. The results reveal three findings. First, the total and dynamic power are 2.53 µW and 0.072 µW, respectively, and the all-digital implementation achieves the 0.99mm2 area. Second, the average R-peak detection sensitivity/precision rates exceed 97.38%/97.08% on the MIT-BIH Noise Stress Test Database, and inter-patient classification accuracy exceeds 90.1% on the MIT-BIH Arrhythmia Database under a 6 dB signal-to-noise ratio (SNR). Third, the system achieves low computational complexity with only 2063 parameters and 5.5 KB of SRAM.
{"title":"A 1.69µJ Highly Robust Cardiac Arrhythmia Monitoring Processor with Triple-Adaptive QRS Detector and Medically Driven Feature-Fusion Hybrid Neural Networks.","authors":"Weihao Wang, Xuecong Lu, Guangshun Wei, Gexuan Wu, Guanglin Deng, Wenliang Chen, Yunfeng Huang, Kong-Pang Pun, Bing Li","doi":"10.1109/TBCAS.2026.3653683","DOIUrl":"https://doi.org/10.1109/TBCAS.2026.3653683","url":null,"abstract":"<p><p>The detection of arrhythmias is crucial in monitoring cardiac health. However, electrocardiogram (ECG) signals obtained from wearable devices are often compromised by noise, including electrode motion artifacts, baseline wander, and muscle artifacts. This paper addresses these challenges by proposing a highly robust cardiac health monitoring processor featuring a cascaded triple-adaptive QRS detector and medically driven feature-fusion hybrid neural networks (HNN) for arrhythmia classification. The QRS detector uses a self-adaptive triplethreshold mechanism that dynamically correlates duration, RR interval, and error correction thresholds, allowing it to accurately identify QRS complex features in noisy signals, facilitated by event-driven sampling. The HNN arrhythmia classifier combines long short-term memory (LSTM) and artificial neural network (ANN) architectures with three medically driven pathological feature fusion, achieving improved computational efficiency. The prototype is fabricated using the 65-nm CMOS process. The results reveal three findings. First, the total and dynamic power are 2.53 µW and 0.072 µW, respectively, and the all-digital implementation achieves the 0.99mm<sup>2</sup> area. Second, the average R-peak detection sensitivity/precision rates exceed 97.38%/97.08% on the MIT-BIH Noise Stress Test Database, and inter-patient classification accuracy exceeds 90.1% on the MIT-BIH Arrhythmia Database under a 6 dB signal-to-noise ratio (SNR). Third, the system achieves low computational complexity with only 2063 parameters and 5.5 KB of SRAM.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146032294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-22DOI: 10.1109/TBCAS.2026.3656748
Fabiana Del Bono, Nicola Di Trani, Ashley Joubert, Camden Caffey, Andrea Dentis, Danilo Demarchi, Alessandro Grattoni, Paolo Motto Ros
Wireless power transfer (WPT) is a key enabler for long-term operation of implantable medical devices, eliminating the need for percutaneous drivelines and frequent surgical device replacements. This paper presents the design and validation of a fully wireless, rechargeable implantable drug delivery system (nDS) with an integrated power management and control system, specifically developed for use in freely moving animal models. The proposed system consists of a subcutaneous implant with an inductive power receiver and an external, backpack-mounted power transmitter that dynamically adjusts energy delivery in response to real-time implant feedback. A closed-loop power control strategy, implemented via Bluetooth Low Energy (BLE) communication, ensures adaptive power transfer to maintain system efficiency despite coil misalignment and animal movement. Building on a previously characterized inductive link, the present work extends the validation from benchtop characterization to in vivo operation in freely moving rats, demonstrating safe and repeatable wireless battery recharging of an implantable nanofluidic drug delivery system. Across four in vivo recharging sessions, the median average power transfer efficiency during constantcurrent phase was 22.9% with a median average power delivered to the load of 104.7 mW. The charging sessions lasted from 90 (first) to 30 (last) minutes, performed once per week over 4 weeks. The proposed closed-loop WPT implementation enabled reliable battery recharging within clinically relevant time scales while maintaining operation in compliance with thermal safety constraints, thereby supporting chronic, fully untethered drug delivery studies in small animals.
{"title":"In Vivo Wireless Powering of a Long-Acting Nanofluidic Drug Delivery Implant.","authors":"Fabiana Del Bono, Nicola Di Trani, Ashley Joubert, Camden Caffey, Andrea Dentis, Danilo Demarchi, Alessandro Grattoni, Paolo Motto Ros","doi":"10.1109/TBCAS.2026.3656748","DOIUrl":"https://doi.org/10.1109/TBCAS.2026.3656748","url":null,"abstract":"<p><p>Wireless power transfer (WPT) is a key enabler for long-term operation of implantable medical devices, eliminating the need for percutaneous drivelines and frequent surgical device replacements. This paper presents the design and validation of a fully wireless, rechargeable implantable drug delivery system (nDS) with an integrated power management and control system, specifically developed for use in freely moving animal models. The proposed system consists of a subcutaneous implant with an inductive power receiver and an external, backpack-mounted power transmitter that dynamically adjusts energy delivery in response to real-time implant feedback. A closed-loop power control strategy, implemented via Bluetooth Low Energy (BLE) communication, ensures adaptive power transfer to maintain system efficiency despite coil misalignment and animal movement. Building on a previously characterized inductive link, the present work extends the validation from benchtop characterization to in vivo operation in freely moving rats, demonstrating safe and repeatable wireless battery recharging of an implantable nanofluidic drug delivery system. Across four in vivo recharging sessions, the median average power transfer efficiency during constantcurrent phase was 22.9% with a median average power delivered to the load of 104.7 mW. The charging sessions lasted from 90 (first) to 30 (last) minutes, performed once per week over 4 weeks. The proposed closed-loop WPT implementation enabled reliable battery recharging within clinically relevant time scales while maintaining operation in compliance with thermal safety constraints, thereby supporting chronic, fully untethered drug delivery studies in small animals.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146032348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-21DOI: 10.1109/TBCAS.2026.3656160
Jun Wang, Omowuyi Olajide, Akshay Paul, Dinghong Zhang, Jiajia Wu, Yuchen Xu, Yimin Zou, Chul Kim, Gert Cauwenberghs
The demand for high-throughput, multi-modal recording and stimulation in neuroscience research has driven the development of neural interfaces that optimize area and energy efficiency without compromising noise performance. Simultaneously, the need for on-chip data compression to reduce data volume has become increasingly critical. This work presents a neural interface system-on-chip (NISoC) that incorporates 1,024 channels for simultaneous electrical recording and stimulation, enabling high-resolution, high-throughput electrophysiology with record noise-energy efficiency. The 2 mm × 2 mm NISoC, fabricated using 65 nm CMOS technology, integrates a 32 × 32 array of electrodes vertically coupled to analog front-ends. These front-ends support both voltage and current clamping through a programmable interface, providing a voltage range up to 100 dB and a current range of 120 dB. Each channel operates at a power consumption of 0.81 µW, achieving an input-referred voltage noise of 8.8 µVrms over a signal bandwidth from DC to 12.5 kHz. The NISoC also integrates on-chip data acquisition through a back-end array of 32 dynamic incremental SAR ADCs, achieving 25 Msps and 11 effective number of bits (ENOB) acquisition with an energy efficiency of 2 fJ/level. The dynamic incremental SAR ADC architecture further offers additional functionality of intrinsic spike detection for future on-chip neural data compression.
{"title":"A 1024-Channel Hybrid Voltage/Current-Clamp Neural Interface System-on-Chip with Dynamic Incremental SAR Acquisition.","authors":"Jun Wang, Omowuyi Olajide, Akshay Paul, Dinghong Zhang, Jiajia Wu, Yuchen Xu, Yimin Zou, Chul Kim, Gert Cauwenberghs","doi":"10.1109/TBCAS.2026.3656160","DOIUrl":"https://doi.org/10.1109/TBCAS.2026.3656160","url":null,"abstract":"<p><p>The demand for high-throughput, multi-modal recording and stimulation in neuroscience research has driven the development of neural interfaces that optimize area and energy efficiency without compromising noise performance. Simultaneously, the need for on-chip data compression to reduce data volume has become increasingly critical. This work presents a neural interface system-on-chip (NISoC) that incorporates 1,024 channels for simultaneous electrical recording and stimulation, enabling high-resolution, high-throughput electrophysiology with record noise-energy efficiency. The 2 mm × 2 mm NISoC, fabricated using 65 nm CMOS technology, integrates a 32 × 32 array of electrodes vertically coupled to analog front-ends. These front-ends support both voltage and current clamping through a programmable interface, providing a voltage range up to 100 dB and a current range of 120 dB. Each channel operates at a power consumption of 0.81 µW, achieving an input-referred voltage noise of 8.8 µV<sub>rms</sub> over a signal bandwidth from DC to 12.5 kHz. The NISoC also integrates on-chip data acquisition through a back-end array of 32 dynamic incremental SAR ADCs, achieving 25 Msps and 11 effective number of bits (ENOB) acquisition with an energy efficiency of 2 fJ/level. The dynamic incremental SAR ADC architecture further offers additional functionality of intrinsic spike detection for future on-chip neural data compression.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146021170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-20DOI: 10.1109/TBCAS.2026.3654961
Geunchang Seong, Jaeouk Cho, Heeyoung Jung, Minjae Kim, Dongyeol Seok, Su Yeon Jeon, Seonae Jang, Changhoon Sung, Ul Gyu Han, Seongjun Park, Young Sang Cho, Chul Kim
Continuous neural signal acquisition during electrical stimulation is essential for neuromodulation; nevertheless, it is often hindered by high-amplitude stimulation artifacts (SAs). This study presents a neuromodulation system with an application-specific integrated circuit (ASIC) that implements 2.9× faster adaptation than a fixed parameter method for the real-time recovery of neural signals fully overlapped with stimulation artifacts in both time and frequency domains, without any prior calibration. The onchip SA removal module leverages an adaptive infinite impulse response (IIR)-based template-subtraction method with zero-multiplier operation and low computational complexity, enabling rapid template convergence and high accuracy under time-varying SAs while optimizing area and power efficiency. The stimulator incorporates a stimulation frequency dithering mechanism to minimize neural signal loss at the stimulation frequency and its harmonics during recovery. In vitro and in vivo experimental validation, including local field potential (LFP) and action potential (AP) recordings, demonstrated real-time SA removal, achieving 40 dB reduction of SA component and preserving neural signal integrity. The ASIC, fabricated using the TSMC 65nm CMOS LP process, occupies a total die area of 1 mm2. The SA removal module including on-chip memory occupies 0.15 mm2 and consumes 1.3μW. The presented system enables recovery of neural signals obscured by time-varying SAs in real time, without requiring prior calibration or external processing units.
{"title":"A Neuromodulation System with Real-Time Neural Signals Recovery Overlapped Temporally and Spectrally with Stimulation Artifacts.","authors":"Geunchang Seong, Jaeouk Cho, Heeyoung Jung, Minjae Kim, Dongyeol Seok, Su Yeon Jeon, Seonae Jang, Changhoon Sung, Ul Gyu Han, Seongjun Park, Young Sang Cho, Chul Kim","doi":"10.1109/TBCAS.2026.3654961","DOIUrl":"https://doi.org/10.1109/TBCAS.2026.3654961","url":null,"abstract":"<p><p>Continuous neural signal acquisition during electrical stimulation is essential for neuromodulation; nevertheless, it is often hindered by high-amplitude stimulation artifacts (SAs). This study presents a neuromodulation system with an application-specific integrated circuit (ASIC) that implements 2.9× faster adaptation than a fixed parameter method for the real-time recovery of neural signals fully overlapped with stimulation artifacts in both time and frequency domains, without any prior calibration. The onchip SA removal module leverages an adaptive infinite impulse response (IIR)-based template-subtraction method with zero-multiplier operation and low computational complexity, enabling rapid template convergence and high accuracy under time-varying SAs while optimizing area and power efficiency. The stimulator incorporates a stimulation frequency dithering mechanism to minimize neural signal loss at the stimulation frequency and its harmonics during recovery. In vitro and in vivo experimental validation, including local field potential (LFP) and action potential (AP) recordings, demonstrated real-time SA removal, achieving 40 dB reduction of SA component and preserving neural signal integrity. The ASIC, fabricated using the TSMC 65nm CMOS LP process, occupies a total die area of 1 mm<sup>2</sup>. The SA removal module including on-chip memory occupies 0.15 mm<sup>2</sup> and consumes 1.3μW. The presented system enables recovery of neural signals obscured by time-varying SAs in real time, without requiring prior calibration or external processing units.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146014101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-14DOI: 10.1109/TBCAS.2026.3654620
Mark Daniel Alea, Maria Atalaia Rosa, Michael Kraft, Kris Myny, Georges Gielen
This paper presents the design of a high-resolution fully-integrated tactile sensor system, called DERMIS, implemented in a flexible thin-film transistor (TFT) technology for large-area electronic skins. It discusses how an end-to-end design strategy - from the sensor to the readout and to the on-chip feature extraction - enables efficient system reconfiguration to implement a first-of-its-kind and biologically-inspired grasp-state-adaptive tactile sensor. In contrast to existing tactile sensors that only detect slip, the DERMIS system also measures key contact cues, including friction, contact onset/offset, and lift-off onset/offset, enabled by a novel differential capacitive sensorstructure that independently senses shear and normal forces and a co-designed front end that directly extracts both components at the analog domain. Furthermore, due to the analog-based encoding of these grasp-state-dependent contact parameters, the system avoids the use of complex offline slip-extraction algorithms. The per-taxel (tactile pixel) readout consumes a state-of-the-art 72 µW power consumption and occupies 0.36 mm2 area while achieving a human-like 2 mNRMS force resolution at 0.6 mm pitch. This work demonstrates our solution for the first time in a true large-area prototype of 9×4 mm2.
{"title":"DERMIS: End-to-End Design of a Fully Integrated Large-Area Grasp-State-Adaptive Tactile Sensor System on a-IGZO TFT.","authors":"Mark Daniel Alea, Maria Atalaia Rosa, Michael Kraft, Kris Myny, Georges Gielen","doi":"10.1109/TBCAS.2026.3654620","DOIUrl":"https://doi.org/10.1109/TBCAS.2026.3654620","url":null,"abstract":"<p><p>This paper presents the design of a high-resolution fully-integrated tactile sensor system, called DERMIS, implemented in a flexible thin-film transistor (TFT) technology for large-area electronic skins. It discusses how an end-to-end design strategy - from the sensor to the readout and to the on-chip feature extraction - enables efficient system reconfiguration to implement a first-of-its-kind and biologically-inspired grasp-state-adaptive tactile sensor. In contrast to existing tactile sensors that only detect slip, the DERMIS system also measures key contact cues, including friction, contact onset/offset, and lift-off onset/offset, enabled by a novel differential capacitive sensorstructure that independently senses shear and normal forces and a co-designed front end that directly extracts both components at the analog domain. Furthermore, due to the analog-based encoding of these grasp-state-dependent contact parameters, the system avoids the use of complex offline slip-extraction algorithms. The per-taxel (tactile pixel) readout consumes a state-of-the-art 72 µW power consumption and occupies 0.36 mm<sup>2</sup> area while achieving a human-like 2 mN<sub>RMS</sub> force resolution at 0.6 mm pitch. This work demonstrates our solution for the first time in a true large-area prototype of 9×4 mm<sup>2</sup>.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145986148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-12DOI: 10.1109/TBCAS.2026.3652501
Sebastian Frey, Giusy Spacone, Andrea Cossettini, Marco Guermandi, Philipp Schilk, Luca Benini, Victor Kartsch
The growing demand for continuous physiological monitoring and human-machine interaction in realworld settings calls for wearable platforms that are flexible, low-power, and capable of on-device intelligence. This work presents BioGAP-Ultra, an advanced multimodal biosensing platform that supports synchronized acquisition of diverse electrophysiological and hemodynamic signals such as EEG, EMG, ECG, and PPG while enabling embedded AI processing at state-of-the-art energy efficiency. BioGAP-Ultra is a major extension of our previous BioGAP design aimed at meeting the rapidly growing requirements of wearable biosensing applications. It features (i) increased on-device storage (×2 SRAM, ×4 FLASH), (ii) improved wireless connectivity (supporting up to 1.4 Mbit/s bandwidth, ×4 higher than BioGAP), (iii) enhanced number of signal modalities (from 3 to 5) and analog input channels (×2). Further, it is accompanied by a real-time visualization and analysis software suite that supports the hardware design, providing access to raw data and real-time configurability on a mobile phone. Finally, we demonstrate the system's versatility through integration into various wearable form factors: an EEG-PPG headband consuming 32.8 mW, an EMG sleeve at 26.7 mW, and an ECG-PPG chestband requiring only 9.3 mW for continuous acquisition and streaming, tailored for diverse biosignal applications. To showcase its edge-AI capabilities, we further deploy two representative on device applications: (1) ECG-PPG-based PAT estimation at 8.6 mW, and (2) EMG-ACC-based classification of reach-and grasp motion phases, achieving 79.9 % ± 5.7 % accuracy at 23.6 mW. All hardware and software design files are also released open-source with a permissive license.
{"title":"BioGAP-Ultra: A Modular Edge-AI Platform for Wearable Multimodal Biosignal Acquisition and Processing.","authors":"Sebastian Frey, Giusy Spacone, Andrea Cossettini, Marco Guermandi, Philipp Schilk, Luca Benini, Victor Kartsch","doi":"10.1109/TBCAS.2026.3652501","DOIUrl":"https://doi.org/10.1109/TBCAS.2026.3652501","url":null,"abstract":"<p><p>The growing demand for continuous physiological monitoring and human-machine interaction in realworld settings calls for wearable platforms that are flexible, low-power, and capable of on-device intelligence. This work presents BioGAP-Ultra, an advanced multimodal biosensing platform that supports synchronized acquisition of diverse electrophysiological and hemodynamic signals such as EEG, EMG, ECG, and PPG while enabling embedded AI processing at state-of-the-art energy efficiency. BioGAP-Ultra is a major extension of our previous BioGAP design aimed at meeting the rapidly growing requirements of wearable biosensing applications. It features (i) increased on-device storage (×2 SRAM, ×4 FLASH), (ii) improved wireless connectivity (supporting up to 1.4 Mbit/s bandwidth, ×4 higher than BioGAP), (iii) enhanced number of signal modalities (from 3 to 5) and analog input channels (×2). Further, it is accompanied by a real-time visualization and analysis software suite that supports the hardware design, providing access to raw data and real-time configurability on a mobile phone. Finally, we demonstrate the system's versatility through integration into various wearable form factors: an EEG-PPG headband consuming 32.8 mW, an EMG sleeve at 26.7 mW, and an ECG-PPG chestband requiring only 9.3 mW for continuous acquisition and streaming, tailored for diverse biosignal applications. To showcase its edge-AI capabilities, we further deploy two representative on device applications: (1) ECG-PPG-based PAT estimation at 8.6 mW, and (2) EMG-ACC-based classification of reach-and grasp motion phases, achieving 79.9 % ± 5.7 % accuracy at 23.6 mW. All hardware and software design files are also released open-source with a permissive license.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145961024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}