Palagiri Veera Reddy, V. V. Satyanarayana Tallapragada
{"title":"使用整数自适应压缩器的 FPGA 无损心电信号压缩系统","authors":"Palagiri Veera Reddy, V. V. Satyanarayana Tallapragada","doi":"10.1007/s10470-024-02269-w","DOIUrl":null,"url":null,"abstract":"<div><p>The most common non-invasive diagnostic model is the Electrocardiogram (ECG), which records the heart’s electrical activity over time and is used to diagnose various heart conditions. Due to the requirements of a typical eHealth system, it is necessary to compress ECG signals for long-term data recording and remote transmission. Moreover, cardiovascular diseases (CVDs) have been considered the most long-lasting disorders in recent years. The transmission of information from the patient to the distant hospital is necessary because rapid analysis and treatment are essential for the condition to be cured. Also, the data must be in the form of lossless and high-predictability data. So, the goal of this study was to create a two-stage lossless Integer Adaptive Predictor (IAP) compressor that could be implemented on a Field Programmable Gate Array (FPGA) without introducing any data loss during the compression process. Before compression, the ECG signals are denoised using a Fast Normalized Least Mean Square (FNLMS) algorithm-based adaptive filter, which removes the undesirable noise presented in the signal. Here, the adaptive filter is designed based on the hybrid systolic folding structure and compressor-based multiplier architecture to minimize the power, delay and area consumption of the filter while performing the signal-denoising process. Xilinx and MATLAB are used to run simulations using the MIT-BIH Arrhythmia and PTB diagnostic databases. Several performance parameters are used to assess the proposed design’s efficacy, and the results are compared to those of similar current designs. Consequently, the proposed compressor achieves a 45.23% compression ratio (CR) on MIT-BIH and a 10.87% average CR on the PTB diagnostic database, which demonstrates that the compression proficiency of the proposed design is high.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"119 2","pages":"331 - 361"},"PeriodicalIF":1.2000,"publicationDate":"2024-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"FPGA-enabled lossless ECG signal compression system using an integer adaptive compressor\",\"authors\":\"Palagiri Veera Reddy, V. V. Satyanarayana Tallapragada\",\"doi\":\"10.1007/s10470-024-02269-w\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>The most common non-invasive diagnostic model is the Electrocardiogram (ECG), which records the heart’s electrical activity over time and is used to diagnose various heart conditions. Due to the requirements of a typical eHealth system, it is necessary to compress ECG signals for long-term data recording and remote transmission. Moreover, cardiovascular diseases (CVDs) have been considered the most long-lasting disorders in recent years. The transmission of information from the patient to the distant hospital is necessary because rapid analysis and treatment are essential for the condition to be cured. Also, the data must be in the form of lossless and high-predictability data. So, the goal of this study was to create a two-stage lossless Integer Adaptive Predictor (IAP) compressor that could be implemented on a Field Programmable Gate Array (FPGA) without introducing any data loss during the compression process. Before compression, the ECG signals are denoised using a Fast Normalized Least Mean Square (FNLMS) algorithm-based adaptive filter, which removes the undesirable noise presented in the signal. Here, the adaptive filter is designed based on the hybrid systolic folding structure and compressor-based multiplier architecture to minimize the power, delay and area consumption of the filter while performing the signal-denoising process. Xilinx and MATLAB are used to run simulations using the MIT-BIH Arrhythmia and PTB diagnostic databases. Several performance parameters are used to assess the proposed design’s efficacy, and the results are compared to those of similar current designs. Consequently, the proposed compressor achieves a 45.23% compression ratio (CR) on MIT-BIH and a 10.87% average CR on the PTB diagnostic database, which demonstrates that the compression proficiency of the proposed design is high.</p></div>\",\"PeriodicalId\":7827,\"journal\":{\"name\":\"Analog Integrated Circuits and Signal Processing\",\"volume\":\"119 2\",\"pages\":\"331 - 361\"},\"PeriodicalIF\":1.2000,\"publicationDate\":\"2024-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Analog Integrated Circuits and Signal Processing\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10470-024-02269-w\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-024-02269-w","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
FPGA-enabled lossless ECG signal compression system using an integer adaptive compressor
The most common non-invasive diagnostic model is the Electrocardiogram (ECG), which records the heart’s electrical activity over time and is used to diagnose various heart conditions. Due to the requirements of a typical eHealth system, it is necessary to compress ECG signals for long-term data recording and remote transmission. Moreover, cardiovascular diseases (CVDs) have been considered the most long-lasting disorders in recent years. The transmission of information from the patient to the distant hospital is necessary because rapid analysis and treatment are essential for the condition to be cured. Also, the data must be in the form of lossless and high-predictability data. So, the goal of this study was to create a two-stage lossless Integer Adaptive Predictor (IAP) compressor that could be implemented on a Field Programmable Gate Array (FPGA) without introducing any data loss during the compression process. Before compression, the ECG signals are denoised using a Fast Normalized Least Mean Square (FNLMS) algorithm-based adaptive filter, which removes the undesirable noise presented in the signal. Here, the adaptive filter is designed based on the hybrid systolic folding structure and compressor-based multiplier architecture to minimize the power, delay and area consumption of the filter while performing the signal-denoising process. Xilinx and MATLAB are used to run simulations using the MIT-BIH Arrhythmia and PTB diagnostic databases. Several performance parameters are used to assess the proposed design’s efficacy, and the results are compared to those of similar current designs. Consequently, the proposed compressor achieves a 45.23% compression ratio (CR) on MIT-BIH and a 10.87% average CR on the PTB diagnostic database, which demonstrates that the compression proficiency of the proposed design is high.
期刊介绍:
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.