Performance improvement of enhancement-mode GaN-based HEMT power devices by employing a vertical gate structure and composite interlayers*

In this work, p-n junction vertical gate (JVG) and polarization junction vertical gate (PVG) structures are for the first time proposed to improve the performance of GaN-based enhancement-mode (E-mode) high electron mobility transistor (HEMT) devices. Compared with the control group featuring the vertical gate structure, a highly improved threshold voltage (V _th) and breakdown voltage (BV) are achieved with the assistance of the extended depletion regions formed by inserting single or composite interlayers. The structure dimensions and physical parameters for device interlayers are optimized by TCAD simulation to adjust the spatial electric field distribution and hence improve the device off-state characteristics. The optimal JVG-HEMT device can reach a V _th of 3.4 V, a low on-state resistance (R _on) of 0.64 mΩ cm², and a BV of 1245 V, while the PVG-HEMT device exhibits a V _th of 3.7 V, an R _on of 0.65 mΩ cm², and a BV of 1184 V, which could be further boosted when an additional field plate design is employed. Thus, the figure-of-merit value of JVG- and PVG-HEMT devices rise to 2.4 and 2.2 GW cm⁻², respectively, much higher than that for the VG-HEMT control group (1.0 GW cm⁻²). This work provides a novel technical approach to realize higher-performance E-mode HEMTs.