{"title":"设计基于 Dibit 的 XOR 和 XNOR 门的替代方法","authors":"Surajit Bosu, Baibaswata Bhattacharjee","doi":"10.29292/jics.v19i1.794","DOIUrl":null,"url":null,"abstract":"In this generation, high-speed communication has very demanding. In this respect, optical communication plays a crucial role in meeting the goal of high-speed communication. With the increasing demands of high-speed communication, huge data processing is also needed. Therefore, we have proposed a design of XOR and XNOR gates using five reflective semiconductor optical amplifiers (RSOA). Our proposed gates are dibit logic-based. To increase the reliability of the devise, we have incorporated this logic scheme. Here, we consider the logic state ‘0’ for the absence of pulse and logic state ‘1’ for the presence of pulse. The dibit logic ‘0 1’ and ‘1 0’ are similar as ‘0’ and ‘1’ in digtal states, respectively. To check its practical feasibility, we have simulated the proposed design in Matlabsoftware and also quality factor, contrast, and extinction ratios are calculated for this design.","PeriodicalId":39974,"journal":{"name":"Journal of Integrated Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Alternative approach to design Dibit-based XOR and XNOR gate\",\"authors\":\"Surajit Bosu, Baibaswata Bhattacharjee\",\"doi\":\"10.29292/jics.v19i1.794\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this generation, high-speed communication has very demanding. In this respect, optical communication plays a crucial role in meeting the goal of high-speed communication. With the increasing demands of high-speed communication, huge data processing is also needed. Therefore, we have proposed a design of XOR and XNOR gates using five reflective semiconductor optical amplifiers (RSOA). Our proposed gates are dibit logic-based. To increase the reliability of the devise, we have incorporated this logic scheme. Here, we consider the logic state ‘0’ for the absence of pulse and logic state ‘1’ for the presence of pulse. The dibit logic ‘0 1’ and ‘1 0’ are similar as ‘0’ and ‘1’ in digtal states, respectively. To check its practical feasibility, we have simulated the proposed design in Matlabsoftware and also quality factor, contrast, and extinction ratios are calculated for this design.\",\"PeriodicalId\":39974,\"journal\":{\"name\":\"Journal of Integrated Circuits and Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2024-03-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Integrated Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.29292/jics.v19i1.794\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"Engineering\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Integrated Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.29292/jics.v19i1.794","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Engineering","Score":null,"Total":0}
Alternative approach to design Dibit-based XOR and XNOR gate
In this generation, high-speed communication has very demanding. In this respect, optical communication plays a crucial role in meeting the goal of high-speed communication. With the increasing demands of high-speed communication, huge data processing is also needed. Therefore, we have proposed a design of XOR and XNOR gates using five reflective semiconductor optical amplifiers (RSOA). Our proposed gates are dibit logic-based. To increase the reliability of the devise, we have incorporated this logic scheme. Here, we consider the logic state ‘0’ for the absence of pulse and logic state ‘1’ for the presence of pulse. The dibit logic ‘0 1’ and ‘1 0’ are similar as ‘0’ and ‘1’ in digtal states, respectively. To check its practical feasibility, we have simulated the proposed design in Matlabsoftware and also quality factor, contrast, and extinction ratios are calculated for this design.
期刊介绍:
This journal will present state-of-art papers on Integrated Circuits and Systems. It is an effort of both Brazilian Microelectronics Society - SBMicro and Brazilian Computer Society - SBC to create a new scientific journal covering Process and Materials, Device and Characterization, Design, Test and CAD of Integrated Circuits and Systems. The Journal of Integrated Circuits and Systems is published through Special Issues on subjects to be defined by the Editorial Board. Special issues will publish selected papers from both Brazilian Societies annual conferences, SBCCI - Symposium on Integrated Circuits and Systems and SBMicro - Symposium on Microelectronics Technology and Devices.